FSL DMA engine transfer to PCI memory

Scott Wood scottwood at freescale.com
Wed Jan 26 06:57:06 EST 2011

On Tue, 25 Jan 2011 16:34:49 +0000
David Laight <David.Laight at ACULAB.COM> wrote:

> > > >>>> custom board based on P2020 running linux-2.6.35. The PCI
> > > >>>> device is Altera FPGA, connected directly to SoC PCI-E
> controller.
> > This sounds like your FPGA doesn't handle burst mode accesses 
> > correctly.
> > A logic analyzer will help you prove it.
> He is doing PCIe, not PCI.
> A PCIe transfers is an HDLC packet pair, one containing the
> request, the other the response.
> In order to get any significant throughput the hdlc packet(s)
> have to contain all the data (eg 128 bytes).
> On the ppc we used that means you have to use the dma
> controller inside the PCIe interface block.

What was the ppc you used?

On 85xx/QorIQ-family chips such as P2020, there is no DMA controller
inside the PCIe controller itself (or are you talking about bus
mastering by the PCIe device[1]?  "interface" is a bit ambiguous),
though it was considered part of the PCI controller on 82xx.

The DMA engine and PCIe are both on OCeaN, so the traffic does not need
to pass through the e500 Coherency Module.  My understanding -- for
what it's worth, coming from a software person :-) -- is that you should
be able to get large transfer chunks using the DMA engine.

I suggest getting things working, and then seeing whether the
performance is acceptable.

> The generic dma controller can't even generate 64bit
> cycles into the ppc's PCIe engine.

Could you elaborate?


[1] To the original poster, is there any reason you're not doing bus
mastering from the PCIe device, assuming you control the content of
the FPGA?

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