Flushing data cache on PPC405 in Linux

John Linn John.Linn at xilinx.com
Fri Feb 25 01:15:28 EST 2011

> -----Original Message-----
> From: Dan Malek [mailto:ppc6dev at digitaldans.com]
> Sent: Wednesday, February 23, 2011 8:39 PM
> To: John Linn
> Cc: linuxppc-dev at ozlabs.org
> Subject: Re: Flushing data cache on PPC405 in Linux
> Hi John.
> On Feb 23, 2011, at 5:04 PM, John Linn wrote:
> > Any thoughts?
> I can come up with two methods, but before I describe them
> ensure you consider the actual implementation of your 405 core.
> My comments are based on the "standard" ppc405 processor,
> but since you can configure the embedded cores to your liking,
> the cache size may be different that the 16K bytes on the old
> processor.
> Method one.  Just 'memset()' 16K of data that will replace all cache
> lines and push out modified lines.  This 16K must be physically
> contiguous, so allocate in your favorite way, with with the cache
> coherent DMA functions, bootmem, reserved, whatever.  Just
> ensure that this 16K is also cached, as I've implemented
> dma_cache_coherent into uncached VM space in the past :-)

Awesome Dan, that seems reasonable to me and much easier than I was
thinking :)

I was obviously making it harder than it had to be as usual. Seems like
I can just kmalloc the memory then memset it. 

Appreciate the help and suggestions.

-- John

> Method two.  Use 'dcread' to read the cache tags.  If the line is
> modified, form an EA that will match that line and 'dcbf' the line.
> This is a little more tricky because the tags are physical addresses,
> so you would need to do this with the MMU disabled to ensure
> the physical EA you generated also hits the cache.  The upside
> is you only perform the actual required flush operations, and you
> didn't blow the cache away requiring a refill latency.
> Have fun!
> 	-- Dan

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