Flushing data cache on PPC405 in Linux
ppc6dev at digitaldans.com
Thu Feb 24 14:38:38 EST 2011
On Feb 23, 2011, at 5:04 PM, John Linn wrote:
> Any thoughts?
I can come up with two methods, but before I describe them
ensure you consider the actual implementation of your 405 core.
My comments are based on the "standard" ppc405 processor,
but since you can configure the embedded cores to your liking,
the cache size may be different that the 16K bytes on the old
Method one. Just 'memset()' 16K of data that will replace all cache
lines and push out modified lines. This 16K must be physically
contiguous, so allocate in your favorite way, with with the cache
coherent DMA functions, bootmem, reserved, whatever. Just
ensure that this 16K is also cached, as I've implemented
dma_cache_coherent into uncached VM space in the past :-)
Method two. Use 'dcread' to read the cache tags. If the line is
modified, form an EA that will match that line and 'dcbf' the line.
This is a little more tricky because the tags are physical addresses,
so you would need to do this with the MMU disabled to ensure
the physical EA you generated also hits the cache. The upside
is you only perform the actual required flush operations, and you
didn't blow the cache away requiring a refill latency.
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