[PATCH 12/15] powerpc/book3e: Use way 3 for linear mapping bolted entry

[Kumar Gala]

On Apr 18, 2011, at 4:40 PM, Benjamin Herrenschmidt wrote:

> On Mon, 2011-04-18 at 07:43 -0500, Kumar Gala wrote:
>> On Apr 15, 2011, at 3:32 AM, Michael Ellerman wrote:
>> 
>>> From: Benjamin Herrenschmidt <benh at kernel.crashing.org>
>>> 
>>> An erratum on A2 can lead to the bolted entry we insert for the linear
>>> mapping being evicted, to avoid that write the bolted entry to way 3.
>>> 
>>> Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
>>> Signed-off-by: Michael Ellerman <michael at ellerman.id.au>
>>> ---
>>> arch/powerpc/kernel/exceptions-64e.S |    5 +++--
>>> 1 files changed, 3 insertions(+), 2 deletions(-)
>>> 
>>> diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
>>> index 5c43063..e6c0926 100644
>>> --- a/arch/powerpc/kernel/exceptions-64e.S
>>> +++ b/arch/powerpc/kernel/exceptions-64e.S
>>> @@ -864,8 +864,9 @@ have_hes:
>>> 	 * that will have to be made dependent on whether we are running under
>>> 	 * a hypervisor I suppose.
>>> 	 */
>>> -	ori	r3,r3,MAS0_HES | MAS0_WQ_ALLWAYS
>>> -	mtspr	SPRN_MAS0,r3
>>> +	ori	r11,r3,MAS0_WQ_ALLWAYS
>>> +	oris	r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
>>> +	mtspr	SPRN_MAS0,r11
>>> 	lis	r3,(MAS1_VALID | MAS1_IPROT)@h
>>> 	ori	r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
>>> 	mtspr	SPRN_MAS1,r3
>> 
>> Seems like this should have a MMU Feature bit or something for A2.
> 
> Too early. We haven't detected the CPU and are establishing the initial
> TLB entry here.

How about wrapping with CONFIG_PPC_A2

> Any reason why that wouldn't work on something else anyways ?

No, I wasn't paying attention to what this code exactly was (not enough context in the diff), I see its our initial setup so not a big deal.  Was thinking this was run-time exception handler code.

- k