[PATCH] powerpc/85xx: P1020 DTS : re-organize dts files

Grant Likely grant.likely at secretlab.ca
Thu Apr 7 18:09:09 EST 2011


On Thu, Apr 07, 2011 at 11:55:34AM +0530, Prabhakar Kushwaha wrote:
> Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts
> files for P1020 based systems to use dtsi file.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
> Acked-by: Kumar Gala <kumar.gala at freescale.com>
> ---
>  Based upon git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch master)
> 
>  Please see mpc5200b.dtsi for reference.
>  
>  Tested on P1020RDB

Minor comments below, but I think this looks good.

g.

> 
>  arch/powerpc/boot/dts/p1020rdb.dts |  315 +-----------------------------
>  arch/powerpc/boot/dts/p1020si.dtsi |  378 ++++++++++++++++++++++++++++++++++++
>  2 files changed, 380 insertions(+), 313 deletions(-)
>  create mode 100644 arch/powerpc/boot/dts/p1020si.dtsi
> 
> diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
> index e0668f8..8ae5ddf 100644
> --- a/arch/powerpc/boot/dts/p1020rdb.dts
> +++ b/arch/powerpc/boot/dts/p1020rdb.dts
> @@ -9,12 +9,10 @@
>   * option) any later version.
>   */
>  
> -/dts-v1/;
> +/include/ "p1020si.dtsi"
> +
>  / {
> -	model = "fsl,P1020";

Model here should actually reflect the name of the board, not the soc.
I don't think you want to remove it from here, but it definitely looks
like it needs to be fixed.

>  	compatible = "fsl,P1020RDB";
> -	#address-cells = <2>;
> -	#size-cells = <2>;
>  
>  	aliases {
>  		serial0 = &serial0;
> @@ -26,34 +24,11 @@
>  		pci1 = &pci1;
>  	};
>  
> -	cpus {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
> -		PowerPC,P1020 at 0 {
> -			device_type = "cpu";
> -			reg = <0x0>;
> -			next-level-cache = <&L2>;
> -		};
> -
> -		PowerPC,P1020 at 1 {
> -			device_type = "cpu";
> -			reg = <0x1>;
> -			next-level-cache = <&L2>;
> -		};
> -	};
> -
>  	memory {
>  		device_type = "memory";
>  	};
>  
>  	localbus at ffe05000 {
> -		#address-cells = <2>;
> -		#size-cells = <1>;
> -		compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
> -		reg = <0 0xffe05000 0 0x1000>;
> -		interrupts = <19 2>;
> -		interrupt-parent = <&mpic>;
>  
>  		/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
>  		ranges = <0x0 0x0 0x0 0xef000000 0x01000000
> @@ -165,88 +140,14 @@
>  	};
>  
>  	soc at ffe00000 {
> -		#address-cells = <1>;
> -		#size-cells = <1>;
> -		device_type = "soc";
> -		compatible = "fsl,p1020-immr", "simple-bus";
> -		ranges = <0x0  0x0 0xffe00000 0x100000>;
> -		bus-frequency = <0>;		// Filled out by uboot.
> -
> -		ecm-law at 0 {
> -			compatible = "fsl,ecm-law";
> -			reg = <0x0 0x1000>;
> -			fsl,num-laws = <12>;
> -		};
> -
> -		ecm at 1000 {
> -			compatible = "fsl,p1020-ecm", "fsl,ecm";
> -			reg = <0x1000 0x1000>;
> -			interrupts = <16 2>;
> -			interrupt-parent = <&mpic>;
> -		};
> -
> -		memory-controller at 2000 {
> -			compatible = "fsl,p1020-memory-controller";
> -			reg = <0x2000 0x1000>;
> -			interrupt-parent = <&mpic>;
> -			interrupts = <16 2>;
> -		};
> -
>  		i2c at 3000 {
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			cell-index = <0>;
> -			compatible = "fsl-i2c";
> -			reg = <0x3000 0x100>;
> -			interrupts = <43 2>;
> -			interrupt-parent = <&mpic>;
> -			dfsrr;
>  			rtc at 68 {
>  				compatible = "dallas,ds1339";
>  				reg = <0x68>;
>  			};
>  		};
>  
> -		i2c at 3100 {
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			cell-index = <1>;
> -			compatible = "fsl-i2c";
> -			reg = <0x3100 0x100>;
> -			interrupts = <43 2>;
> -			interrupt-parent = <&mpic>;
> -			dfsrr;
> -		};
> -
> -		serial0: serial at 4500 {
> -			cell-index = <0>;
> -			device_type = "serial";
> -			compatible = "ns16550";
> -			reg = <0x4500 0x100>;
> -			clock-frequency = <0>;
> -			interrupts = <42 2>;
> -			interrupt-parent = <&mpic>;
> -		};
> -
> -		serial1: serial at 4600 {
> -			cell-index = <1>;
> -			device_type = "serial";
> -			compatible = "ns16550";
> -			reg = <0x4600 0x100>;
> -			clock-frequency = <0>;
> -			interrupts = <42 2>;
> -			interrupt-parent = <&mpic>;
> -		};
> -
>  		spi at 7000 {
> -			cell-index = <0>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			compatible = "fsl,espi";
> -			reg = <0x7000 0x1000>;
> -			interrupts = <59 0x2>;
> -			interrupt-parent = <&mpic>;
> -			mode = "cpu";
>  
>  			fsl_m25p80 at 0 {
>  				#address-cells = <1>;
> @@ -294,66 +195,7 @@
>  			};
>  		};
>  
> -		gpio: gpio-controller at f000 {
> -			#gpio-cells = <2>;
> -			compatible = "fsl,mpc8572-gpio";
> -			reg = <0xf000 0x100>;
> -			interrupts = <47 0x2>;
> -			interrupt-parent = <&mpic>;
> -			gpio-controller;
> -		};
> -
> -		L2: l2-cache-controller at 20000 {
> -			compatible = "fsl,p1020-l2-cache-controller";
> -			reg = <0x20000 0x1000>;
> -			cache-line-size = <32>;	// 32 bytes
> -			cache-size = <0x40000>; // L2,256K
> -			interrupt-parent = <&mpic>;
> -			interrupts = <16 2>;
> -		};
> -
> -		dma at 21300 {
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			compatible = "fsl,eloplus-dma";
> -			reg = <0x21300 0x4>;
> -			ranges = <0x0 0x21100 0x200>;
> -			cell-index = <0>;
> -			dma-channel at 0 {
> -				compatible = "fsl,eloplus-dma-channel";
> -				reg = <0x0 0x80>;
> -				cell-index = <0>;
> -				interrupt-parent = <&mpic>;
> -				interrupts = <20 2>;
> -			};
> -			dma-channel at 80 {
> -				compatible = "fsl,eloplus-dma-channel";
> -				reg = <0x80 0x80>;
> -				cell-index = <1>;
> -				interrupt-parent = <&mpic>;
> -				interrupts = <21 2>;
> -			};
> -			dma-channel at 100 {
> -				compatible = "fsl,eloplus-dma-channel";
> -				reg = <0x100 0x80>;
> -				cell-index = <2>;
> -				interrupt-parent = <&mpic>;
> -				interrupts = <22 2>;
> -			};
> -			dma-channel at 180 {
> -				compatible = "fsl,eloplus-dma-channel";
> -				reg = <0x180 0x80>;
> -				cell-index = <3>;
> -				interrupt-parent = <&mpic>;
> -				interrupts = <23 2>;
> -			};
> -		};
> -
>  		mdio at 24000 {
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			compatible = "fsl,etsec2-mdio";
> -			reg = <0x24000 0x1000 0xb0030 0x4>;
>  
>  			phy0: ethernet-phy at 0 {
>  				interrupt-parent = <&mpic>;
> @@ -369,10 +211,6 @@
>  		};
>  
>  		mdio at 25000 {
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			compatible = "fsl,etsec2-tbi";
> -			reg = <0x25000 0x1000 0xb1030 0x4>;
>  
>  			tbi0: tbi-phy at 11 {
>  				reg = <0x11>;
> @@ -381,97 +219,25 @@
>  		};
>  
>  		enet0: ethernet at b0000 {
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			device_type = "network";
> -			model = "eTSEC";
> -			compatible = "fsl,etsec2";
> -			fsl,num_rx_queues = <0x8>;
> -			fsl,num_tx_queues = <0x8>;
> -			local-mac-address = [ 00 00 00 00 00 00 ];
> -			interrupt-parent = <&mpic>;
>  			fixed-link = <1 1 1000 0 0>;
>  			phy-connection-type = "rgmii-id";
>  
> -			queue-group at 0 {
> -				#address-cells = <1>;
> -				#size-cells = <1>;
> -				reg = <0xb0000 0x1000>;
> -				interrupts = <29 2 30 2 34 2>;
> -			};
> -
> -			queue-group at 1 {
> -				#address-cells = <1>;
> -				#size-cells = <1>;
> -				reg = <0xb4000 0x1000>;
> -				interrupts = <17 2 18 2 24 2>;
> -			};
>  		};
>  
>  		enet1: ethernet at b1000 {
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			device_type = "network";
> -			model = "eTSEC";
> -			compatible = "fsl,etsec2";
> -			fsl,num_rx_queues = <0x8>;
> -			fsl,num_tx_queues = <0x8>;
> -			local-mac-address = [ 00 00 00 00 00 00 ];
> -			interrupt-parent = <&mpic>;
>  			phy-handle = <&phy0>;
>  			tbi-handle = <&tbi0>;
>  			phy-connection-type = "sgmii";
>  
> -			queue-group at 0 {
> -				#address-cells = <1>;
> -				#size-cells = <1>;
> -				reg = <0xb1000 0x1000>;
> -				interrupts = <35 2 36 2 40 2>;
> -			};
> -
> -			queue-group at 1 {
> -				#address-cells = <1>;
> -				#size-cells = <1>;
> -				reg = <0xb5000 0x1000>;
> -				interrupts = <51 2 52 2 67 2>;
> -			};
>  		};
>  
>  		enet2: ethernet at b2000 {
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			device_type = "network";
> -			model = "eTSEC";
> -			compatible = "fsl,etsec2";
> -			fsl,num_rx_queues = <0x8>;
> -			fsl,num_tx_queues = <0x8>;
> -			local-mac-address = [ 00 00 00 00 00 00 ];
> -			interrupt-parent = <&mpic>;
>  			phy-handle = <&phy1>;
>  			phy-connection-type = "rgmii-id";
>  
> -			queue-group at 0 {
> -				#address-cells = <1>;
> -				#size-cells = <1>;
> -				reg = <0xb2000 0x1000>;
> -				interrupts = <31 2 32 2 33 2>;
> -			};
> -
> -			queue-group at 1 {
> -				#address-cells = <1>;
> -				#size-cells = <1>;
> -				reg = <0xb6000 0x1000>;
> -				interrupts = <25 2 26 2 27 2>;
> -			};
>  		};
>  
>  		usb at 22000 {
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			compatible = "fsl-usb2-dr";
> -			reg = <0x22000 0x1000>;
> -			interrupt-parent = <&mpic>;
> -			interrupts = <28 0x2>;
>  			phy_type = "ulpi";
>  		};
>  
> @@ -481,82 +247,15 @@
>  		   it enables USB2. OTOH, U-Boot does create a new node
>  		   when there isn't any. So, just comment it out.
>  		usb at 23000 {
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			compatible = "fsl-usb2-dr";
> -			reg = <0x23000 0x1000>;
> -			interrupt-parent = <&mpic>;
> -			interrupts = <46 0x2>;
>  			phy_type = "ulpi";
>  		};
>  		*/
>  
> -		sdhci at 2e000 {
> -			compatible = "fsl,p1020-esdhc", "fsl,esdhc";
> -			reg = <0x2e000 0x1000>;
> -			interrupts = <72 0x2>;
> -			interrupt-parent = <&mpic>;
> -			/* Filled in by U-Boot */
> -			clock-frequency = <0>;
> -		};
> -
> -		crypto at 30000 {
> -			compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
> -				     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
> -			reg = <0x30000 0x10000>;
> -			interrupts = <45 2 58 2>;
> -			interrupt-parent = <&mpic>;
> -			fsl,num-channels = <4>;
> -			fsl,channel-fifo-len = <24>;
> -			fsl,exec-units-mask = <0xbfe>;
> -			fsl,descriptor-types-mask = <0x3ab0ebf>;
> -		};
> -
> -		mpic: pic at 40000 {
> -			interrupt-controller;
> -			#address-cells = <0>;
> -			#interrupt-cells = <2>;
> -			reg = <0x40000 0x40000>;
> -			compatible = "chrp,open-pic";
> -			device_type = "open-pic";
> -		};
> -
> -		msi at 41600 {
> -			compatible = "fsl,p1020-msi", "fsl,mpic-msi";
> -			reg = <0x41600 0x80>;
> -			msi-available-ranges = <0 0x100>;
> -			interrupts = <
> -				0xe0 0
> -				0xe1 0
> -				0xe2 0
> -				0xe3 0
> -				0xe4 0
> -				0xe5 0
> -				0xe6 0
> -				0xe7 0>;
> -			interrupt-parent = <&mpic>;
> -		};
> -
> -		global-utilities at e0000 {	//global utilities block
> -			compatible = "fsl,p1020-guts";
> -			reg = <0xe0000 0x1000>;
> -			fsl,has-rstcr;
> -		};
>  	};
>  
>  	pci0: pcie at ffe09000 {
> -		compatible = "fsl,mpc8548-pcie";
> -		device_type = "pci";
> -		#interrupt-cells = <1>;
> -		#size-cells = <2>;
> -		#address-cells = <3>;
> -		reg = <0 0xffe09000 0 0x1000>;
> -		bus-range = <0 255>;
>  		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
>  			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
> -		clock-frequency = <33333333>;
> -		interrupt-parent = <&mpic>;
> -		interrupts = <16 2>;
>  		pcie at 0 {
>  			reg = <0x0 0x0 0x0 0x0 0x0>;
>  			#size-cells = <2>;
> @@ -573,18 +272,8 @@
>  	};
>  
>  	pci1: pcie at ffe0a000 {
> -		compatible = "fsl,mpc8548-pcie";
> -		device_type = "pci";
> -		#interrupt-cells = <1>;
> -		#size-cells = <2>;
> -		#address-cells = <3>;
> -		reg = <0 0xffe0a000 0 0x1000>;
> -		bus-range = <0 255>;
>  		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
>  			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
> -		clock-frequency = <33333333>;
> -		interrupt-parent = <&mpic>;
> -		interrupts = <16 2>;
>  		pcie at 0 {
>  			reg = <0x0 0x0 0x0 0x0 0x0>;
>  			#size-cells = <2>;
> diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
> new file mode 100644
> index 0000000..7b87d00
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/p1020si.dtsi
> @@ -0,0 +1,378 @@
> +/*
> + * P1020si Device Tree Source
> + *
> + * Copyright 2011 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +/ {
> +	model = "fsl,P1020";
> +	compatible = "fsl,P1020";

I think you should drop both of these properties from the include
file.  Leave it to the board to actually define them.

> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		PowerPC,P1020 at 0 {
> +			device_type = "cpu";
> +			reg = <0x0>;
> +			next-level-cache = <&L2>;
> +		};
> +
> +		PowerPC,P1020 at 1 {
> +			device_type = "cpu";
> +			reg = <0x1>;
> +			next-level-cache = <&L2>;
> +		};
> +	};
> +
> +	localbus at ffe05000 {
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
> +		reg = <0 0xffe05000 0 0x1000>;
> +		interrupts = <19 2>;
> +		interrupt-parent = <&mpic>;
> +	};
> +
> +	soc at ffe00000 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		device_type = "soc";
> +		compatible = "fsl,p1020-immr", "simple-bus";
> +		ranges = <0x0  0x0 0xffe00000 0x100000>;
> +		bus-frequency = <0>;		// Filled out by uboot.
> +
> +		ecm-law at 0 {
> +			compatible = "fsl,ecm-law";
> +			reg = <0x0 0x1000>;
> +			fsl,num-laws = <12>;
> +		};
> +
> +		ecm at 1000 {
> +			compatible = "fsl,p1020-ecm", "fsl,ecm";
> +			reg = <0x1000 0x1000>;
> +			interrupts = <16 2>;
> +			interrupt-parent = <&mpic>;
> +		};
> +
> +		memory-controller at 2000 {
> +			compatible = "fsl,p1020-memory-controller";
> +			reg = <0x2000 0x1000>;
> +			interrupt-parent = <&mpic>;
> +			interrupts = <16 2>;
> +		};
> +
> +		i2c at 3000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			cell-index = <0>;
> +			compatible = "fsl-i2c";
> +			reg = <0x3000 0x100>;
> +			interrupts = <43 2>;
> +			interrupt-parent = <&mpic>;
> +			dfsrr;
> +		};
> +
> +		i2c at 3100 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			cell-index = <1>;
> +			compatible = "fsl-i2c";
> +			reg = <0x3100 0x100>;
> +			interrupts = <43 2>;
> +			interrupt-parent = <&mpic>;
> +			dfsrr;
> +		};
> +
> +		serial0: serial at 4500 {
> +			cell-index = <0>;
> +			device_type = "serial";
> +			compatible = "ns16550";
> +			reg = <0x4500 0x100>;
> +			clock-frequency = <0>;
> +			interrupts = <42 2>;
> +			interrupt-parent = <&mpic>;
> +		};
> +
> +		serial1: serial at 4600 {
> +			cell-index = <1>;
> +			device_type = "serial";
> +			compatible = "ns16550";
> +			reg = <0x4600 0x100>;
> +			clock-frequency = <0>;
> +			interrupts = <42 2>;
> +			interrupt-parent = <&mpic>;
> +		};
> +
> +		spi at 7000 {
> +			cell-index = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "fsl,espi";
> +			reg = <0x7000 0x1000>;
> +			interrupts = <59 0x2>;
> +			interrupt-parent = <&mpic>;
> +			mode = "cpu";
> +		};
> +
> +		gpio: gpio-controller at f000 {
> +			#gpio-cells = <2>;
> +			compatible = "fsl,mpc8572-gpio";
> +			reg = <0xf000 0x100>;
> +			interrupts = <47 0x2>;
> +			interrupt-parent = <&mpic>;
> +			gpio-controller;
> +		};
> +
> +		L2: l2-cache-controller at 20000 {
> +			compatible = "fsl,p1020-l2-cache-controller";
> +			reg = <0x20000 0x1000>;
> +			cache-line-size = <32>;	// 32 bytes
> +			cache-size = <0x40000>; // L2,256K
> +			interrupt-parent = <&mpic>;
> +			interrupts = <16 2>;
> +		};
> +
> +		dma at 21300 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "fsl,eloplus-dma";
> +			reg = <0x21300 0x4>;
> +			ranges = <0x0 0x21100 0x200>;
> +			cell-index = <0>;
> +			dma-channel at 0 {
> +				compatible = "fsl,eloplus-dma-channel";
> +				reg = <0x0 0x80>;
> +				cell-index = <0>;
> +				interrupt-parent = <&mpic>;
> +				interrupts = <20 2>;
> +			};
> +			dma-channel at 80 {
> +				compatible = "fsl,eloplus-dma-channel";
> +				reg = <0x80 0x80>;
> +				cell-index = <1>;
> +				interrupt-parent = <&mpic>;
> +				interrupts = <21 2>;
> +			};
> +			dma-channel at 100 {
> +				compatible = "fsl,eloplus-dma-channel";
> +				reg = <0x100 0x80>;
> +				cell-index = <2>;
> +				interrupt-parent = <&mpic>;
> +				interrupts = <22 2>;
> +			};
> +			dma-channel at 180 {
> +				compatible = "fsl,eloplus-dma-channel";
> +				reg = <0x180 0x80>;
> +				cell-index = <3>;
> +				interrupt-parent = <&mpic>;
> +				interrupts = <23 2>;
> +			};
> +		};
> +
> +		mdio at 24000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "fsl,etsec2-mdio";
> +			reg = <0x24000 0x1000 0xb0030 0x4>;
> +
> +		};
> +
> +		mdio at 25000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "fsl,etsec2-tbi";
> +			reg = <0x25000 0x1000 0xb1030 0x4>;
> +
> +		};
> +
> +		enet0: ethernet at b0000 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			device_type = "network";
> +			model = "eTSEC";
> +			compatible = "fsl,etsec2";
> +			fsl,num_rx_queues = <0x8>;
> +			fsl,num_tx_queues = <0x8>;
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			interrupt-parent = <&mpic>;
> +
> +			queue-group at 0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0xb0000 0x1000>;
> +				interrupts = <29 2 30 2 34 2>;
> +			};
> +
> +			queue-group at 1 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0xb4000 0x1000>;
> +				interrupts = <17 2 18 2 24 2>;
> +			};
> +		};
> +
> +		enet1: ethernet at b1000 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			device_type = "network";
> +			model = "eTSEC";
> +			compatible = "fsl,etsec2";
> +			fsl,num_rx_queues = <0x8>;
> +			fsl,num_tx_queues = <0x8>;
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			interrupt-parent = <&mpic>;
> +
> +			queue-group at 0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0xb1000 0x1000>;
> +				interrupts = <35 2 36 2 40 2>;
> +			};
> +
> +			queue-group at 1 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0xb5000 0x1000>;
> +				interrupts = <51 2 52 2 67 2>;
> +			};
> +		};
> +
> +		enet2: ethernet at b2000 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			device_type = "network";
> +			model = "eTSEC";
> +			compatible = "fsl,etsec2";
> +			fsl,num_rx_queues = <0x8>;
> +			fsl,num_tx_queues = <0x8>;
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			interrupt-parent = <&mpic>;
> +
> +			queue-group at 0 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0xb2000 0x1000>;
> +				interrupts = <31 2 32 2 33 2>;
> +			};
> +
> +			queue-group at 1 {
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0xb6000 0x1000>;
> +				interrupts = <25 2 26 2 27 2>;
> +			};
> +		};
> +
> +		usb at 22000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "fsl-usb2-dr";
> +			reg = <0x22000 0x1000>;
> +			interrupt-parent = <&mpic>;
> +			interrupts = <28 0x2>;
> +		};
> +
> +		/* USB2 is shared with localbus, so it must be disabled
> +		   by default. We can't put 'status = "disabled";' here
> +		   since U-Boot doesn't clear the status property when
> +		   it enables USB2. OTOH, U-Boot does create a new node
> +		   when there isn't any. So, just comment it out.
> +		usb at 23000 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "fsl-usb2-dr";
> +			reg = <0x23000 0x1000>;
> +			interrupt-parent = <&mpic>;
> +			interrupts = <46 0x2>;
> +			phy_type = "ulpi";
> +		};
> +		*/
> +
> +		sdhci at 2e000 {
> +			compatible = "fsl,p1020-esdhc", "fsl,esdhc";
> +			reg = <0x2e000 0x1000>;
> +			interrupts = <72 0x2>;
> +			interrupt-parent = <&mpic>;
> +			/* Filled in by U-Boot */
> +			clock-frequency = <0>;
> +		};
> +
> +		crypto at 30000 {
> +			compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
> +				     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
> +			reg = <0x30000 0x10000>;
> +			interrupts = <45 2 58 2>;
> +			interrupt-parent = <&mpic>;
> +			fsl,num-channels = <4>;
> +			fsl,channel-fifo-len = <24>;
> +			fsl,exec-units-mask = <0xbfe>;
> +			fsl,descriptor-types-mask = <0x3ab0ebf>;
> +		};
> +
> +		mpic: pic at 40000 {
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +			reg = <0x40000 0x40000>;
> +			compatible = "chrp,open-pic";
> +			device_type = "open-pic";
> +		};
> +
> +		msi at 41600 {
> +			compatible = "fsl,p1020-msi", "fsl,mpic-msi";
> +			reg = <0x41600 0x80>;
> +			msi-available-ranges = <0 0x100>;
> +			interrupts = <
> +				0xe0 0
> +				0xe1 0
> +				0xe2 0
> +				0xe3 0
> +				0xe4 0
> +				0xe5 0
> +				0xe6 0
> +				0xe7 0>;
> +			interrupt-parent = <&mpic>;
> +		};
> +
> +		global-utilities at e0000 {	//global utilities block
> +			compatible = "fsl,p1020-guts";
> +			reg = <0xe0000 0x1000>;
> +			fsl,has-rstcr;
> +		};
> +	};
> +
> +	pci0: pcie at ffe09000 {
> +		compatible = "fsl,mpc8548-pcie";
> +		device_type = "pci";
> +		#interrupt-cells = <1>;
> +		#size-cells = <2>;
> +		#address-cells = <3>;
> +		reg = <0 0xffe09000 0 0x1000>;
> +		bus-range = <0 255>;
> +		clock-frequency = <33333333>;
> +		interrupt-parent = <&mpic>;
> +		interrupts = <16 2>;
> +	};
> +
> +	pci1: pcie at ffe0a000 {
> +		compatible = "fsl,mpc8548-pcie";
> +		device_type = "pci";
> +		#interrupt-cells = <1>;
> +		#size-cells = <2>;
> +		#address-cells = <3>;
> +		reg = <0 0xffe0a000 0 0x1000>;
> +		bus-range = <0 255>;
> +		clock-frequency = <33333333>;
> +		interrupt-parent = <&mpic>;
> +		interrupts = <16 2>;
> +	};
> +};
> -- 
> 1.7.3
> 
> 
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss


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