MPC8641D PCI Endpoint incoming interrupts?

[david.hagood at gmail.com]

I'm trying to use an MPC8641D as a PCIe endpoint device, and I'm trying to
work out how the host root complex CPU can interrupt the PPC core. It's
not very clear how to do all of this, and I'd like some help fitting the
pieces together. If there's a good how-to online I've yet to find it.

As I read it, on the host side, I'd do one of:
1) a write to the PPC's BAR0, offset 0x41400 (MSGR0) with some message value
2) a write to BAR0 offset 0x41600 (MSIR0) and set a bit within it.
3) a write to 0x41740 (MSIIR) to set a bit in MSIR0

So question #1 is "which of those should I use?" (or should I use
something else?)

Then, as I read it, I'd have to somehow convert the interrupt vector the
PIC uses into a virtual interrupt number suitable for request_irq. I've
seen mentions of irq_of_parse_and_map(), but I've not found a good
description of how to use it. Does anybody have any (non-null) pointers on
this?

Once I get to request_irq I'm on familiar ground.