[PATCH 27/27] KVM: PPC: Add Documentation about PV interface

[Alexander Graf]

On 02.07.2010, at 18:27, Segher Boessenkool wrote:

>> +To find out if we're running on KVM or not, we overlay the PVR register. Usually
>> +the PVR register contains an id that identifies your CPU type. If, however, you
>> +pass KVM_PVR_PARA in the register that you want the PVR result in, the register
>> +still contains KVM_PVR_PARA after the mfpvr call.
>> +
>> +	LOAD_REG_IMM(r5, KVM_PVR_PARA)
>> +	mfpvr	r5
>> +	[r5 still contains KVM_PVR_PARA]
> 
> I love this part :-)

:)

> 
>> +	__u64 scratch3;
>> +	__u64 critical;		/* Guest may not get interrupts if == r1 */
>> +	__u64 sprg0;
>> +	__u64 sprg1;
>> +	__u64 sprg2;
>> +	__u64 sprg3;
>> +	__u64 srr0;
>> +	__u64 srr1;
>> +	__u64 dar;
>> +	__u64 msr;
>> +	__u32 dsisr;
>> +	__u32 int_pending;	/* Tells the guest if we have an interrupt */
>> +};
>> +
>> +Additions to the page must only occur at the end. Struct fields are always 32
>> +bit aligned.
> 
> The u64s are 64-bit aligned, should they always be?

That's obvious, isn't it? And the ABI only specifies u64s to be 32 bit aligned, no? At least that's what ld and std specify.

> 
>> +The "ld" and "std" instructions are transormed to "lwz" and "stw" instructions
>> +respectively on 32 bit systems with an added offset of 4 to accomodate for big
>> +endianness.
> 
> Will this add never overflow?  Is there anything that checks for it?

It basically means that to access dar, we either do

ld  rX, DAR(0)

or

lwz rX, DAR+4(0)


> 
>> +mtmsrd	rX, 0		b	<special mtmsr section>
>> +mtmsr			b	<special mtmsr section>
> 
> mtmsr rX

Nod.


Alex