[PATCH 03/13] mpc52xx: add SCLPC register bit definitions

[Grant Likely]

On Tue, Dec 22, 2009 at 12:00 AM, Roman Fietze
<roman.fietze at telemotive.de> wrote:
>

This should probably be merged with the first patch to actually use
the bit definitions.  More comments below.

> Signed-off-by: Roman Fietze <roman.fietze at telemotive.de>
> ---
>  arch/powerpc/include/asm/mpc52xx.h |   40 +++++++++++++++++++++++++++--------
>  1 files changed, 31 insertions(+), 9 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/asm/mpc52xx.h
> index 57f8335..c659d1d 100644
> --- a/arch/powerpc/include/asm/mpc52xx.h
> +++ b/arch/powerpc/include/asm/mpc52xx.h
> @@ -17,6 +17,7 @@
>  #include <asm/types.h>
>  #include <asm/prom.h>
>  #include <asm/mpc5xxx.h>
> +#include <linux/bitops.h>
>  #endif /* __ASSEMBLY__ */
>
>  #include <linux/suspend.h>
> @@ -212,11 +213,34 @@ struct mpc52xx_sclpc {
>
>        u32 fifo_data;          /* 0x40 FIFO data word register */
>        u32 fifo_status;        /* 0x44 FIFO status register */
> -       u8 fifo_control;        /* 0x48 FIFO control register */
> -       u8 reserved2[3];
> +       u32 fifo_control;       /* 0x48 FIFO control register */
>        u32 fifo_alarm;         /* 0x4C FIFO alarm register */
>  };
>
> +#define MPC52xx_SCLPC_FIFO_SIZE                        (0x200)         /* FIFO size 512 bytes */
> +
> +#define MPC52xx_SCLPC_CONTROL_CS(cs)           ((uint32_t)(cs) << 24)  /* CSX bits */
> +#define MPC52xx_SCLPC_CONTROL_FLUSH            BIT(17)         /* flush, used in last packet  */
> +#define MPC52xx_SCLPC_CONTROL_RWB_RECEIVE      BIT(16)         /* RWb bit, 1 = receive */
> +#define MPC52xx_SCLPC_CONTROL_DAI              BIT(8)
> +
> +#define MPC52xx_SCLPC_ENABLE_RC                        BIT(24)         /* reset controller bit */
> +#define MPC52xx_SCLPC_ENABLE_RF                        BIT(16)         /* reset FIFO bit */
> +#define MPC52xx_SCLPC_ENABLE_AIE               BIT(9)          /* abort interrupt enable bit */
> +#define MPC52xx_SCLPC_ENABLE_NIE               BIT(8)          /* normal interrupt enable bit */
> +#define MPC52xx_SCLPC_ENABLE_ME                        BIT(0)          /* master enable bit */
> +
> +#define MPC52xx_SCLPC_PACKET_SIZE_RESTART      BIT(24)
> +
> +#define MPC52xx_SCLPC_STATUS_AT                        BIT(28)         /* abort termination */
> +#define MPC52xx_SCLPC_STATUS_NT                        BIT(24)         /* normal termination */
> +#define MPC52xx_SCLPC_STATUS_BYTES_DONE_MASK   (0x00FFFFFFU)   /* bytes done bit mask */
> +
> +#define MPC52xx_SLPC_FIFO_STATUS_ERR           BIT(22) /* error bit */
> +
> +#define MPC52xx_SLPC_FIFO_CONTROL_GR(gr)       ((gr) << 24)    /* granularity bits */
> +
> +
>  /* Clock Distribution control */
>  struct mpc52xx_cdm {
>        u32 jtag_id;            /* CDM + 0x00  reg0 read only */
> @@ -304,19 +328,18 @@ extern void mpc52xx_restart(char *cmd);
>  struct mpc52xx_gpt_priv;
>  extern struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq);
>  extern int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
> -                            int continuous);
> +                                  int continuous);

Unrelated whitespace change?

>  extern u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt);
>  extern int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt);
>
>  /* mpc52xx_lpbfifo.c */
>  #define MPC52XX_LPBFIFO_FLAG_READ              (0)
> -#define MPC52XX_LPBFIFO_FLAG_WRITE             (1<<0)
> -#define MPC52XX_LPBFIFO_FLAG_NO_INCREMENT      (1<<1)
> -#define MPC52XX_LPBFIFO_FLAG_NO_DMA            (1<<2)
> -#define MPC52XX_LPBFIFO_FLAG_POLL_DMA          (1<<3)
> +#define MPC52XX_LPBFIFO_FLAG_WRITE             BIT(0)
> +#define MPC52XX_LPBFIFO_FLAG_NO_INCREMENT      BIT(1)
> +#define MPC52XX_LPBFIFO_FLAG_NO_DMA            BIT(2)
> +#define MPC52XX_LPBFIFO_FLAG_POLL_DMA          BIT(3)

I prefer the (1<<n) style myself.

>
>  struct mpc52xx_lpbfifo_request {
> -       struct list_head list;

Why is the list head being removed?

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.