MPC831x (and others?) NAND erase performance improvements

[Joakim Tjernlund]

"David Laight" <David.Laight at ACULAB.COM> wrote on 2010/12/13 09:33:37:
>
>
> > > An external IRQ line would let you limit interrupts to rising edges
> > > rather than all edges, though you'd lose the ability to
> > > directly read the line status.
> >
> > oh, one cannot read the IRQ line? didn't know that. Also I not sure
> > all Freescale CPUs can do rising edge.
>
> I suspect that you may be able to leave the interupt masked, but still
> read the 'interrupt pending' register. Which would have the same effect.

Ah, that should work too. I should be able to read the 'interrupt pending'
register at all times, even when it isn't masked.

What if one has several NAND chips to build a big FS? Is the NAND
controller equipped to handle that?

>
> Our HW engineers tend to feed everything into an FPGA since it
> gives than a lot more flexibility over pin connections.
> In which case the invertor is trivial.
> (and the fpga interface can read the status!)

Yes, but not all of our boards have FPGA and we load the FPGA
from the SW so it is a chicken and egg problem for us.

     Jocke