MPC831x (and others?) NAND erase performance improvements

[David Laight]

> > An external IRQ line would let you limit interrupts to rising edges
> > rather than all edges, though you'd lose the ability to 
> > directly read the line status.
> 
> oh, one cannot read the IRQ line? didn't know that. Also I not sure
> all Freescale CPUs can do rising edge.

I suspect that you may be able to leave the interupt masked, but still
read the 'interrupt pending' register. Which would have the same effect.

Our HW engineers tend to feed everything into an FPGA since it
gives than a lot more flexibility over pin connections.
In which case the invertor is trivial.
(and the fpga interface can read the status!)

	David