MPC831x (and others?) NAND erase performance improvements

[Joakim Tjernlund]

Scott Wood <scottwood at freescale.com> wrote on 2010/12/08 23:25:59:
>
> On Wed, 8 Dec 2010 17:02:45 -0500
> Mark Mason <mason at postdiluvian.org> wrote:
>
> > I don't think that using a software NAND controller instead of the LBC
> > FCM mode is all that bad.  Again, I haven't actually done it, so check
> > the MTD docs, but I'm pretty sure the software is meant to do that, so
> > it doesn't even really constitute a "fix".  Assuming that it is
> > supported then I doubt that configuring the NAND layer to use your
> > setup would be any harder than configuring the FCM.
>
> The MTD layer supports some really simple NAND controllers, but what do
> you mean by not having a controller at all?  Hooking everything up to
> GPIO?  Using UPM?
>
> There is already a UPM NAND driver, BTW.
>
> You would lose hardware ECC and the ability to be interrupt-driven (the
> latter should be possible with SW changes, using GPIO interrupts).

Good, using SW ECC isn't really a choice, I rather switch to another CPU that
can do NAND in HW(are any other Freescale CPU:s that can do this ?).
We haven't started our design yet so we still have this option. I would need to
know if the GPIO solution works well enough with the NAND controller though.
I will ask our Freescale contact about that.

Thanks for sharing this info,
                                Jocke