[PATCH v3 3/3] powerpc/fsl: 85xx: add cache-sram support

[Kumar Gala]

On Nov 19, 2009, at 11:45 AM, Scott Wood wrote:

> On Thu, Nov 19, 2009 at 08:29:19AM -0600, Kumar Gala wrote:
>>>> +config FSL_85XX_CACHE_SRAM_BASE
>>>> +	hex
>>>> +	depends on FSL_85XX_CACHE_SRAM
>>>> +	default "0xfff00000"
>>>> +
>>>
>>> I really don't like setting the physical address this way, can we
>>> not do this via the device tree?
>>
>> At a high level I think we should add something like the following in
>> the .dts:
>>
>> sram at fff00000 {
>> 	fsl,sram-ctrl-handle = <&L2>;
>> 	reg = <0xfff00000 0xNNNN>;
>> 	compatible = "fsl,mpc85xx-l2-sram";
>> }
>>
>> the NNNN can be the size the sram is configured as.
>
> I don't see why this needs to go in the device tree, if it's the  
> kernel
> that is setting it up.  The kernel can pick any address and size it
> wants.

It can, we just don't normally do physical address allocation in the  
kernel.  I just dont want it as a compile time thing.  Either .dts or  
make it runtime allocated by the kernel.

- k