[PATCH 0/8] 8xx: Misc fixes for buggy insn

[Scott Wood]

Joakim Tjernlund wrote:
> Scott Wood <scottwood at freescale.com> wrote on 12/11/2009 20:45:59:
>> One other concern with pinning on 8xx -- could it cause problems with
>> uncached DMA mappings?  What happens if a speculative load pulls in a
>> cache line in an area that's supposed to be uncached?
> 
> hmm, why should this be a problem?

Because then you would be accessing potentially stale DMA data -- and 
more generally, the architecture prohibits such mixing.

> Pinning has been around as a config option
> for a long time so any problems should have surfaced by now.

It has existed as an option, which is going to get less test coverage 
than something that is always on.  Plus, it would not be a particularly 
common failure -- easy to blame one-off weirdness on something else.

> Secondly, I was thinking that we could just make the ITLB pinning
> mandatory and let the DTLB pinning be as is, configurable.

That could work.  We could also limit the pool of memory 
dma_alloc_coherent() uses to not overlap with anything pinned.

-Scott