[PATCH 0/8] 8xx: Misc fixes for buggy insn

[Joakim Tjernlund]

Scott Wood <scottwood at freescale.com> wrote on 12/11/2009 20:45:59:
>
> Joakim Tjernlund wrote:
> > Scott Wood <scottwood at freescale.com> wrote on 11/11/2009 16:26:53:
> >> On Wed, Nov 11, 2009 at 01:06:10AM +0100, Joakim Tjernlund wrote:
> >>> Scott Wood <scottwood at freescale.com> wrote on 11/11/2009 00:21:18:
> >>>> Where would you put the dcbi?  How do you regain control after that
> >>>> cache line has been refilled, but before code flows back to the bad branch?
> >>> The dcbi would replace the current CPU15 tlbie.
> >> But that only works if you take an ITLB miss at the right time.
> >
> > Yeah, I misread the CPU15 errata so my ideas will not work.
> >
> > Anyhow, will you send a patch that make TLB pinning mandatory?
> > After that my series can go in.
>
> One other concern with pinning on 8xx -- could it cause problems with
> uncached DMA mappings?  What happens if a speculative load pulls in a
> cache line in an area that's supposed to be uncached?

hmm, why should this be a problem? Pinning has been around as a config option
for a long time so any problems should have surfaced by now.

Secondly, I was thinking that we could just make the ITLB pinning
mandatory and let the DTLB pinning be as is, configurable.

 Jocke