issue at the beginning of kernel booting

Fri Mar 27 19:36:28 EST 2009

there is something confused me, which is my kernel code is halt because of something wrong i have no hint about it.
my bootloader is u-boot, version is 1.1.4, kernel version is 2.6.14.1, processor is MPC8247.
u-boot have run on the board already. bootloader booting information as follow:
U-Boot 1.1.4 (Mar 22 2009 - 20:30:57)
MPC8272 Reset Status: External Soft, External Hard
MPC8272 Clock Configuration
&nbsp;- Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq&nbsp; 25-75 , Core Freq 100-300
&nbsp;- dfbrg 1, corecnf 0x1a, busdf 3, cpmdf 1, plldf 0, pllmf 3
&nbsp;- vco_out&nbsp; 400000000, scc_clk&nbsp; 100000000, brg_clk&nbsp;&nbsp; 25000000
&nbsp;- cpu_clk&nbsp; 400000000, cpm_clk&nbsp; 200000000, bus_clk&nbsp; 100000000
Board: Motorola MPC8272ADS
DRAM:&nbsp; 32 MB
FLASH: 512 kB
In:&nbsp;&nbsp;&nbsp; serial
Out:&nbsp;&nbsp; serial
Err:&nbsp;&nbsp; serial
Net:&nbsp;&nbsp; FCC1 ETHERNET
Hit any key to stop autoboot:&nbsp; 0 
then i "tftp uImage" and "bootm" with no parameters, i suppose that booting kernel will be normal at beginning even if there is no any parameters. 
=> tftp
Using FCC1 ETHERNET device
TFTP from server 192.168.0.99; our IP address is 192.168.0.100
Filename 'uImage'.
Load address: 0x400000
Loading: #################################################################
&nbsp; #################################################################
&nbsp; ########################################################
done
Bytes transferred = 952157 (e875d hex)
=> bootm
## Booting image at 00400000 ...
&nbsp;&nbsp; Image Name:&nbsp;&nbsp; Linux-2.6.14
&nbsp;&nbsp; Image Type:&nbsp;&nbsp; PowerPC Linux Kernel Image (gzip compressed)
&nbsp;&nbsp; Data Size:&nbsp;&nbsp;&nbsp; 952093 Bytes = 929.8 kB
&nbsp;&nbsp; Load Address: 00000000
&nbsp;&nbsp; Entry Point:&nbsp; 00000000
&nbsp;&nbsp; Verifying Checksum ... OK
OK
&nbsp;
by LEDs i am sure that it surely performs in kernel. then by sequence early_init, mmu_off, clear_bats and flush_tlbs.
at call_setup_cpu, the performing is halt, i get "bl call_setup_cpu" will invoke setup_common_caches actually. right here, enable caches for 603e by HID0, get HID0 register and setting DCE and ICE bit put into HID0 register, the performing halt. 
_GLOBAL(__setup_cpu_603)
&nbsp;b&nbsp;setup_common_caches
setup_common_caches:
&nbsp;mfspr&nbsp;r11,SPRN_HID0
&nbsp;andi.&nbsp;r0,r11,HID0_DCE
&nbsp;ori&nbsp;r11,r11,HID0_ICE|HID0_DCE
&nbsp;ori&nbsp;r8,r11,HID0_ICFI
&nbsp;bne&nbsp;1f&nbsp;&nbsp;&nbsp;/* don't invalidate the D-cache */
/* halt here */&nbsp;
&nbsp;ori&nbsp;r8,r8,HID0_DCI&nbsp;&nbsp;/* unless it wasn't enabled */
1:&nbsp;sync
&nbsp;mtspr&nbsp;SPRN_HID0,r8&nbsp;&nbsp;/* enable and invalidate caches */
&nbsp;sync
&nbsp;mtspr&nbsp;SPRN_HID0,r11&nbsp;&nbsp;/* enable caches */
&nbsp;sync
&nbsp;isync
&nbsp;blr
then after i clear HI0_DCI , performing will run till MSR[DR] is set, i clear that bit. will run again. 
i have nerver changed the code because i think there is something be independent of my board device. isnt?
why the performing halt there ? or do you think there is something wrong in the front?
Cheers~ 
Sauce

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