issue at the beginning of kernel booting

chmhou chmhou at sina.com
Fri Mar 27 19:36:28 EST 2009


there is something confused me, which is my kernel code is halt because of something wrong i have no hint about it.
my bootloader is u-boot, version is 1.1.4, kernel version is 2.6.14.1, processor is MPC8247.
u-boot have run on the board already. bootloader booting information as follow:
U-Boot 1.1.4 (Mar 22 2009 - 20:30:57)
MPC8272 Reset Status: External Soft, External Hard
MPC8272 Clock Configuration
 - Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq  25-75 , Core Freq 100-300
 - dfbrg 1, corecnf 0x1a, busdf 3, cpmdf 1, plldf 0, pllmf 3
 - vco_out  400000000, scc_clk  100000000, brg_clk   25000000
 - cpu_clk  400000000, cpm_clk  200000000, bus_clk  100000000
Board: Motorola MPC8272ADS
DRAM:  32 MB
FLASH: 512 kB
In:    serial
Out:   serial
Err:   serial
Net:   FCC1 ETHERNET
Hit any key to stop autoboot:  0 
then i "tftp uImage" and "bootm" with no parameters, i suppose that booting kernel will be normal at beginning even if there is no any parameters. 
=> tftp
Using FCC1 ETHERNET device
TFTP from server 192.168.0.99; our IP address is 192.168.0.100
Filename 'uImage'.
Load address: 0x400000
Loading: #################################################################
  #################################################################
  ########################################################
done
Bytes transferred = 952157 (e875d hex)
=> bootm
## Booting image at 00400000 ...
   Image Name:   Linux-2.6.14
   Image Type:   PowerPC Linux Kernel Image (gzip compressed)
   Data Size:    952093 Bytes = 929.8 kB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
OK
 
by LEDs i am sure that it surely performs in kernel. then by sequence early_init, mmu_off, clear_bats and flush_tlbs.
at call_setup_cpu, the performing is halt, i get "bl call_setup_cpu" will invoke setup_common_caches actually. right here, enable caches for 603e by HID0, get HID0 register and setting DCE and ICE bit put into HID0 register, the performing halt. 
_GLOBAL(__setup_cpu_603)
 b setup_common_caches
setup_common_caches:
 mfspr r11,SPRN_HID0
 andi. r0,r11,HID0_DCE
 ori r11,r11,HID0_ICE|HID0_DCE
 ori r8,r11,HID0_ICFI
 bne 1f   /* don't invalidate the D-cache */
/* halt here */ 
 ori r8,r8,HID0_DCI  /* unless it wasn't enabled */
1: sync
 mtspr SPRN_HID0,r8  /* enable and invalidate caches */
 sync
 mtspr SPRN_HID0,r11  /* enable caches */
 sync
 isync
 blr
then after i clear HI0_DCI , performing will run till MSR[DR] is set, i clear that bit. will run again. 
i have nerver changed the code because i think there is something be independent of my board device. isnt?
why the performing halt there ? or do you think there is something wrong in the front?
Cheers~ 
Sauce

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