Device Tree setup for 8272-based board
Daniel Ng
daniel.ng1234 at gmail.com
Wed Jan 21 18:37:32 EST 2009
Hi Scott,
On Wed, Jan 21, 2009 at 3:41 AM, Scott Wood <scottwood at freescale.com> wrote:
> On Tue, Jan 20, 2009 at 06:23:08PM +1100, Daniel Ng wrote:
>> PID hash table entries: 128 (order: 7, 512 bytes)
>> time_init: decrementer frequency = 16.500000 MHz
>> time_init: processor frequency = 330.000000 MHz
>> clocksource: timebase mult[f26c9b2] shift[22] registered
>> clockevent: decrementer mult[439] shift[16] cpu[0]
>> Console: colour dummy ü
>>
>> -at this point the board just reboots.
>
> Looks like something goes wrong when the real serial driver kicks in.
I've managed to enable more debug and see the following boot sequence:
cpm_uart_init_port()
OF: ** translation for device /soc at f0000000/cpm at 119c0/serial at 11a00 **
OF: bus is default (na=1, ns=1) on /soc at f0000000/cpm at 119c0
OF: translating address: 00011a00
OF: parent bus is default (na=1, ns=1) on /soc at f0000000
OF: no ranges, 1:1 translation
OF: parent translation for: 00000000
OF: with offset: 11a00
OF: one level translation: 00011a00
OF: parent bus is default (na=1, ns=1) on /
OF: walking ranges...
OF: default map, cp=0, s=53000, da=11a00
OF: parent translation for: f0000000
OF: with offset: 11a00
OF: one level translation: f0011a00
OF: reached root node
OF: ** translation for device /soc at f0000000/cpm at 119c0/serial at 11a00 **
OF: bus is default (na=1, ns=1) on /soc at f0000000/cpm at 119c0
OF: translating address: 00008000
OF: parent bus is default (na=1, ns=1) on /soc at f0000000
OF: no ranges, 1:1 translation
OF: parent translation for: 00000000
OF: with offset: 8000
OF: one level translation: 00008000
OF: parent bus is default (na=1, ns=1) on /
OF: walking ranges...
OF: default map, cp=0, s=53000, da=8000
OF: parent translation for: f0000000
OF: with offset: 8000
OF: one level translation: f0008000
OF: reached root node
of_irq_map_one: dev=/soc at f0000000/cpm at 119c0/serial at 11a00, index=0
intsize=2 intlen=2
of_irq_map_raw:
par=/soc at f0000000/interrupt-controller at 10c00,intspec=[0x00000028 0x
00000008...],ointsize=2
of_irq_map_raw: ipar=/soc at f0000000/interrupt-controller at 10c00, size=2
-> addrsize=1
-> got it !
irq: irq_create_mapping(0xc02d1320, 0x28)
irq: -> using host @c02d1320
irq: -> obtained virq 40
cpm2_pic_host_map(40, 0x28)
of_get_gpio exited with status -2
of_get_gpio exited with status -2
of_get_gpio exited with status -2
of_get_gpio exited with status -2
of_get_gpio exited with status -2
of_get_gpio exited with status -2
cpm_uart_request_port()
CPM uart[þ
I think the of_get_gpio() error messages are a result of the following
code in cpm_uart_init_port()-
for (i = 0; i < NUM_GPIOS; i++)
pinfo->gpios[i] = of_get_gpio(np, i);
-why is this code here? Is it for processing modem control lines? I
know our board doesn't make use of the modem control lines for
ttyCPM0. Therefore, have I misconfigured something in the Device Tree?
Here's the relevant part of the Device Tree-
cpm at 119c0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
reg = <0x119c0 0x30>;
ranges;
muram at 0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x10000>;
data at 0 {
compatible = "fsl,cpm-muram-data";
reg = <0x0 0x2000 0x9800 0x800>;
};
};
brg at 119f0 {
compatible = "fsl,mpc8272-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <0x119f0 0x10 0x115f0 0x10>;
};
serial at 11a00 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
reg = <0x11a00 0x20 0x8000 0x100>;
interrupts = <40 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0x800000>;
};
};
PIC: interrupt-controller at 10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x10c00 0x80>;
compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
};
Would you please explain what the following lines mean, so I can use
some more appropriate values for my particular board?-
1) In the serial at 11a00 node-
a) reg = <0x11a00 0x20 0x8000 0x100>;
b) interrupts = <40 8>;
c) fsl,cpm-brg = <1>;
d) fsl,cpm-command = <0x800000>;
2) In the brg at 119f0 node-
reg = <0x119f0 0x10 0x115f0 0x10>;
3) In the PIC: interrupt-controller at 10c00 node-
reg = <0x10c00 0x80>;
I have read the relevant documentation under Documentation/powerpc and
Documentation/powerpc/dts-bindings, but these do not seem to go into
enough detail eg.
Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt says the
following about the reg property-
- reg : There may be an arbitrary number of reg resources; BRG
numbers are assigned to these in order.
-> does this mean that each number represents a BRG register? So there
can be a maximum of 1+8=9 reg values, since there are 8 BRG registers?
As for Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt, there
is no explanation at all for what the 'reg', 'interrupts', 'brg' and
'command' values mean... Am I missing something obvious?
Similarly for Documentation/powerpc/dts-bindings/fsl/cpm_qe/pic.txt,
there is no explanation of the 'reg' value. Also, it mentions a
'second interrupt cell' but I only see one in the example it gives.
Here is what it says-
* Interrupt Controllers
Currently defined compatibles:
- fsl,cpm1-pic
- only one interrupt cell
- fsl,pq1-pic
- fsl,cpm2-pic
- second interrupt cell is level/sense:
- 2 is falling edge
- 8 is active low
Example:
interrupt-controller at 10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
compatible = "mpc8272-pic", "fsl,cpm2-pic";
};
Does the level/sense refer to ALL interrupts?
Cheers,
Daniel
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