How does map_flash_by_law1 work?

[向宇]

I'm reading the start.S for mpc83xx in u-boot.
I couldn't understand how the source code below work:
 
/***************************************************
map_flash_by_law1: /* When booting from ROM (Flash or EPROM), clear the  */ /* Address Mask in OR0 so ROM appears everywhere      */ /*----------------------------------------------------*/ lis r3, (CFG_IMMR)@h  /* r3 <= CFG_IMMR    */ lwz r4, OR0 at l(r3) li r5, 0x7fff        /* r5 <= 0x00007FFFF */ and r4, r4, r5 stw r4, OR0 at l(r3)     /* OR0 <= OR0 & 0x00007FFFF */
 
 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,  * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]  * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot  * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is  * 0xFF800.  From the hard resetting to here, the processor fetched and  * executed the instructions one by one.  There is not absolutely  * jumping happened.  Laterly, the u-boot code has to do an absolutely  * jumping to tell the CPU instruction fetching component what the  * u-boot TEXT base address is.  Because the TEXT base resides in the  * boot ROM memory space, to garantee the code can run smoothly after  * that jumping, we must map in the entire boot ROM by Local Access  * Window.  Sometimes, we desire an non-0x00000 or non-0xFF800 starting  * address for boot ROM, such as 0xFE000000.  In this case, the default  * LBIU Local Access Widow 0 will not cover this memory space.  So, we  * need another window to map in it.  */
 lis r4, (CFG_FLASH_BASE)@h ori r4, r4, (CFG_FLASH_BASE)@l stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */
 /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR1 */ /*0x8000_0000 is used to enable this window*/ /*0x0000_0000-0x0000_0012 is the reserved window size*/ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l li r5, CFG_FLASH_SIZE1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b
 
 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= Flash Size */ blr
********************************************************/
 
the problem is from this segment:
 
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b
 
How it adjust the flash size to the fit size?
I define the CFG_FLASH_SIZE equal 1 in the MPC8313ERDB.h
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