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I'm reading the start.S for mpc83xx in u-boot.<BR>
I couldn't understand how the source code below work:<BR>
<BR>
/***************************************************<BR>
map_flash_by_law1:<BR> /* When booting from ROM (Flash or EPROM), clear the */<BR> /* Address Mask in OR0 so ROM appears everywhere */<BR> /*----------------------------------------------------*/<BR> lis r3, (CFG_IMMR)@h /* r3 <= CFG_IMMR */<BR> lwz r4, <A href="mailto:OR0@l(r3">OR0@l(r3</A>)<BR> li r5, 0x7fff /* r5 <= 0x00007FFFF */<BR> and r4, r4, r5<BR> stw r4, <A href="mailto:OR0@l(r3">OR0@l(r3</A>) /* OR0 <= OR0 & 0x00007FFFF */<BR>
<BR>
/* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,<BR> * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]<BR> * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot<BR> * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is<BR> * 0xFF800. From the hard resetting to here, the processor fetched and<BR> * executed the instructions one by one. There is not absolutely<BR> * jumping happened. Laterly, the u-boot code has to do an absolutely<BR> * jumping to tell the CPU instruction fetching component what the<BR> * u-boot TEXT base address is. Because the TEXT base resides in the<BR> * boot ROM memory space, to garantee the code can run smoothly after<BR> * that jumping, we must map in the entire boot ROM by Local Access<BR> * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting<BR> * address for boot ROM, such as 0xFE000000. In this case, the default<BR> * LBIU Local Access Widow 0 will not cover this memory space. So, we<BR> * need another window to map in it.<BR> */<BR>
<BR> lis r4, (CFG_FLASH_BASE)@h<BR> ori r4, r4, (CFG_FLASH_BASE)@l<BR> stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */<BR>
/* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR1 */<BR> /*0x8000_0000 is used to enable this window*/<BR> /*0x0000_0000-0x0000_0012 is the reserved window size*/<BR> lis r4, (0x80000012)@h<BR> ori r4, r4, (0x80000012)@l<BR> li r5, CFG_FLASH_SIZE<BR>1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */<BR> addi r4, r4, 1<BR> bne 1b<BR>
<BR>
stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= Flash Size */<BR> blr<BR>
********************************************************/<BR>
<BR>
the problem is from this segment:<BR>
<BR>
1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */<BR> addi r4, r4, 1<BR> bne 1b<BR>
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How it adjust the flash size to the fit size?<BR>
I define the CFG_FLASH_SIZE equal 1 in the MPC8313ERDB.h<BR><RTE_TEXT></RTE_TEXT><BR><br /><hr />MSN保护盾，十八般武艺保障MSN安全！ <a href='http://im.live.cn/safe/' target='_new'>现在就下载！</a></body>
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