Can't write value into memory ?(E500 V2)

[Scott Wood]

wilbur.chan wrote:
> 2009/8/27 Scott Wood <scottwood at freescale.com>:
>> Is this under Linux (it is a Linux mailing list...)?  If so, there are
>> better ways of communicating that don't involve clobbering random memory and
>> overlapping userspace TLB mappings.
> 
> Yes, I'm doing this under linux in kernel mode.
> 
> I've used interrupt between cores, to make:
> 
> 1) cpu0  carrys some data to a place (As a matter of fact ,the 'data'
> is a kernel, the 'place' is at 0, and  I'm using kexec..)
> 
> 2) cpu0 writes a 'flag' to a physical address(16M), to indicate that ,
> 
> it has finished the carrying in step 1. And jump to new kernel directly.

OK, so it's not really "under Linux" but "between Linuxes". :-)

Don't forget to clean the cache out on the destination core -- icache is 
not coherent with dcache.

> 3) cpu1 enters the loop by IRQ , checking the 'flag' from time to
> time. If the 'flag' is true, it
> 
> breaks the  loop and jumps to the instruction in new kernel.
> 
> 
>> Do both cores have a mapping with the M bit (memory coherence required) set?
> 
> 
> What do you mean by  M bit set?

There is a bit in MAS2, labelled "M", that you must set when writing the 
TLB entry for the mapping to be coherent across cores.

-Scott