Can't write value into memory ?(E500 V2)

wilbur.chan wilbur512 at
Fri Aug 28 02:27:15 EST 2009

2009/8/27 Scott Wood <scottwood at>:
> Is this under Linux (it is a Linux mailing list...)?  If so, there are
> better ways of communicating that don't involve clobbering random memory and
> overlapping userspace TLB mappings.

Yes, I'm doing this under linux in kernel mode.

I've used interrupt between cores, to make:

1) cpu0  carrys some data to a place (As a matter of fact ,the 'data'
is a kernel, the 'place' is at 0, and  I'm using kexec..)

2) cpu0 writes a 'flag' to a physical address(16M), to indicate that ,

it has finished the carrying in step 1. And jump to new kernel directly.

3) cpu1 enters the loop by IRQ , checking the 'flag' from time to
time. If the 'flag' is true, it

breaks the  loop and jumps to the instruction in new kernel.

> Do both cores have a mapping with the M bit (memory coherence required) set?

What do you mean by  M bit set?

I setup a 1:1 mapping in both cpu0 and cpu1, and invalidate all the
other entries in TLB1 and


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