FPGA IRQ design question

[Eddie Dawydiuk]

Hello,

I'm working on a board based on the Yosemite AMCC 440EP. We have an FPGA 
connected via the PCI bus, and has an IRQ line connected directly to the 440EP. 
The FPGA implements two registers to indicate which core generated the 
interrupt. So now the question is from a design standpoint is it preferable to 
setup the IRQ as a single external IRQ then have each driver request this same 
IRQ. In each ISR the driver is responsible for checking the FPGA registers to 
see if the interrupt is intended for itself. Or would it be preferable to modify 
the lower level irq routines such that multiple software/virtual(not sure what 
the right term is here) irqs are created corresponding to the single external 
IRQ. Then abstract the details of the FPGA interrupt registers from each driver. 
Such that each driver request the proper software/virtual IRQ and requires no 
knowledge of the fpga irq registers. Any comments would be appreciated.

-- 
Best Regards,
________________________________________________________________
  Eddie Dawydiuk, Technologic Systems | voice:  (480) 837-5200
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