[PATCH] Xilinx : Framebuffer Driver: Add PLB support (non-DCR)

[Josh Boyer]

On Thu, Apr 09, 2009 at 04:06:56PM +0200, Roderick Colenbrander wrote:
>On Thu, Apr 9, 2009 at 2:46 PM, Josh Boyer <jwboyer at linux.vnet.ibm.com>wrote:
>> > #define NUM_REGS      2
>> > #define REG_FB_ADDR   0
>> >@@ -112,6 +123,11 @@ struct xilinxfb_drvdata {
>> >
>> >       struct fb_info  info;           /* FB driver info record */
>> >
>> >+      u32             regs_phys;      /* phys. address of the control
>> >+                                              registers */
>>
>> Is this driver usable on the 440 based Xilinx devices?  If so, is it
>> possible
>> to have the physical address of the registers above 4GiB, so is common with
>> almost all the I/O on the other 440 boards?
>>
>>
>The driver works fine on 440 based Xilinx boards (the ML510 I use has a 440
>core). It might be nice to move physical addresses above 4GB for devices but
>in all Xilinx tools and reference designs addresses below 4GB are used for
>periperhals and I think even below 2GB (or even below 1GB). It depends on
>the design.

Right.  The "depends on the design" part is what I'm worried about.  Perhaps
using resource_size_t here is more appropriate, given that designs can change
and put the regs above 4GiB.  That way you can set the Kconfig option
appropriately for both cases.

josh