[patch 2/2] powerpc: optimise smp_wmb
benh at kernel.crashing.org
Thu May 22 06:44:45 EST 2008
On Wed, 2008-05-21 at 22:12 +0200, Segher Boessenkool wrote:
> No idea about POWER6; for CBE, the backend works similar to the
> 970 one.
> Given that the architecture says to use lwsync for cases like this,
> it would be very surprising if it performed (much) worse than eieio,
> eh? ;-) So I think your patch is a win; just wanted to clarify on
> your five-time slowdown number.
It makes sense to use lwsync rather than eieio for smb_wmb() as this is
not supposed to be used to order with cache inhibited storage. It's
really a data barrier used by the kernel for normal cacheable storage.
The main question is do we care if the downgrade to sync on power3 hurts
performances (and does it ?) and what do we do for 32 bits as currently,
no 32 bits implementation has lwsync afaik (though that might not be
true for long).
Also, we don't, I think, have verified that they all properly ignore the
added bit and behave as sync rather than program checking..
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