[PATCH 2/2] POWERPC/fsl-pci: Set relaxed ordering on prefetchable ranges

[Trent Piepho]

Provides a small speedup when accessing pefetchable ranges.  To indicate
that a memory range is prefetchable, mark it in the dts file with 42000000
instead of 02000000.

A powepc pci_controller is allowed three memory ranges, any of which may be
prefetchable.  However, the PCI-PCI bridge configuration space only has one
field for "non-prefetchable memory behind bridge", which has a 32 bit
address, and one field for "prefetchable memory behind bridge", which may
have a 64 bit address.  These are PCI bus addresses, not CPU physical
addresses.

So really you're only allowed one memory range of each type.  And if you
want the range at a PCI address above 32 bits you must make it
prefetchable.

Signed-off-by: Trent Piepho <tpiepho at freescale.com>
---
 arch/powerpc/sysdev/fsl_pci.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 656f914..af0d7e3 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -41,6 +41,9 @@ static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
 	pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
 		(u64)res->start, (u64)size);
 
+	if (res->flags & IORESOURCE_PREFETCH)
+		flags |= 0x10000000; /* enable relaxed ordering */
+
 	for (i = 0; size > 0; i++) {
 		unsigned int bits = min(__ilog2(size),
 					__ffs(pci_addr | phys_addr));
-- 
1.5.4.1