[PATCH 0/5] dynamic detection of gianfar TPIPA

Andy Fleming afleming at freescale.com
Fri Apr 11 09:30:37 EST 2008

On Apr 10, 2008, at 12:51, Paul Gortmaker wrote:

> This patch series consists of some minor cleanups that eventually
> allow us to implement a dynamic assignment of the gianfar TBIPA.
> This was the implementation that Andy and Scott indicated was
> the most desireable solution at the bottom of this discussion:
> http://patchwork.ozlabs.org/linuxppc-embedded/patch?id=12902
> The lead up patches are as follows:
> -dont allocate a phydev for the "ghost" phy that seems to appear
>  on ID 0x1f of all the MDIO bus scans.
> -add in the missing assignment to priv->mii_bus when we assign a
>  phy to the device.
> -cleanup of unnecessary externs that the above change allows us.
> -make the mii_bus->priv point to struct gianfar_mdio_data
> At this point, we can then actually use the phy_map of the mii_bus
> to tell us which MDIO ID we can use for the TBIPA, instead of just
> hard coding 0x1f.

I may be missing something, but I don't think this quite right.

If you have a PHY at 0x1f, this patchset will cause no PHY device to  
be allocated for that address, and you'll actually end up assigning  
TBIPA to be 0x1f again, since there's no PHY there.  Right?  Were you  
able to use this code with a PHY at 0x1f?

I like the idea of passing around priv->mii_bus instead of regs, but I  
think it won't work without becoming unnecessarily unwieldy.  The  
problem is that the TBI PHY is not necessarily accessed through the  
same bus as the PHY.  Each controller has its own TBI PHY, and that  
PHY can only be accessed from *that* controller's MDIO bus.  So if you  
want to configure TSEC2's TBI PHY, you use TSEC2's MDIO regs.  That's  
what gfar_local_mdio_* allowed; they write the *local* controller's  
MDIO regs.  It looks like this code sets up priv->mii_bus to point at  
the bus which holds the PHY, but only TSEC0's bus (on most SoCs) is  
connected to actual PHYs.  So you will only ever be able to configure  
the TBI PHY on TSEC0, which will not allow any of the other TSECs to  
use an SGMII PHY.  Were you able to use other TSECs to connect to an  

We could still pass around an mii_bus reference, but this would  
require creating an mii_bus instance for every single TSEC, which is a  
little heavyweight when we just want to configure the TBI PHY once on  

After some thinking, I went ahead and implemented a patch which isn't  
ideal, but should solve the problems your patches set out to solve.   
I've sent it in a separate message.  If you have some systems with  
SGMII and/or a PHY at 0x1f, please test this patch on them.  I don't  
currently have either.


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