[PATCH 2 of 3] [KVM] Add DCR access information to struct kvm_run

[Josh Boyer]

On Tue, 8 Apr 2008 13:54:41 +1000
David Gibson <dwg at au1.ibm.com> wrote:

> On Mon, Apr 07, 2008 at 10:25:32PM -0500, Hollis Blanchard wrote:
> > On Monday 07 April 2008 20:11:28 David Gibson wrote:
> > > On Mon, Apr 07, 2008 at 03:53:33PM -0500, Hollis Blanchard wrote:
> > > > 1 file changed, 7 insertions(+)
> > > > include/linux/kvm.h |    7 +++++++
> > > >
> > > >
> > > > Device Control Registers are essentially another address space found on
> > > > PowerPC 4xx processors, analogous to PIO on x86. DCRs are always 32 bits,
> > > > and are identified by a 32-bit number.
> > >
> > > Well... 10-bit, actually.
> > 
> > The mtdcrux description in the ppc440x6 user manual says the following:
> > 
> > 	Let the contents of register RA denote a Device Control Register.
> > 	The contents of GPR[RS] are placed into the designated Device Control 
> > Register.
> > 
> > I take that to mean that we must worry about 32 bits worth of DCR numbers. 
> > Perhaps I should say "no more than" rather than "always".
> 
> I think that's less misleading.  mtdcrux is very new, anything which
> only has the mtdcr instruction certainly can't take DCR numbers above
> 10 bits, and I would expect that even on chips with mtdcrux the DCR
> bus is probably still only 10-bits, although it could be extended.

http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/C94B06BE313211B887257110006EFFBD/$file/460migrate.pdf

page 4.  "DCR Address Space Increased to 32 bits".

I realize that the above is for 460 cores, but I would not be surprised
at all if that shows up in a future 440 core.  440x6 already seems to
be a conglomeration of some of the features 460 has.

josh