[PATCH] [POWERPC] Fix interrupt routing and setup of ULI M1575 on FSL boards

[Olof Johansson]

On Tue, Sep 11, 2007 at 01:43:59PM -0500, Becky Bruce wrote:

> >> Maybe it would make more sense for you guys to slice the platforms
> >> differently, and have a common platform for the eval boards you have
> >> with ULi on them instead of grouping it by core used by the processor
> >> on the board.
> >>
> >> (In other words, move 86xx over under 85xx, since there wouldn't be
> >> much
> >> left over anyway).
> >
> > Moving 86xx (classic 74xx core) under 85xx (book e500 core) makes
> > even less sense to me.
> 
> Yeah, that makes *no* sense to me either.  It's an unfortunate  
> artifact of the naming of boards to include the core name.  While the  
> devices and boards may be similar, once you have bookE vs non-bookE  
> cores, they become quite different.

It doesn't make sense if you move 86xx under 85xx right now, no.

What I meant (but didn't write) was more along the lines of forking off
a new platform (I don't know if you have a common code name for the SoC
side, but fsl-whatever) that contains the SoC and board support for the
parts and boards that share much (looks like the latest gen 85xx and
8641 would be candidates).

Looks like the CPM2-based stuff could be candidates for something similar
as well, but there's less activity there so there's less reason to rework
those, I suppose.

Of course, down the road I'm sure there'll be a part that contains 75%
of the current SoC, plus something new. And the next gen after that only
contains the 25% non-shared plus 75% brand new stuff and it all falls
apart. Not knowing your roadmap I have a hard time judging if that's
likely though. :-)


-Olof