[PATCH v6 3/9] add Freescale SerDes PHY support

[Kumar Gala]

On Oct 18, 2007, at 10:04 AM, Li Yang wrote:

> The SerDes(serializer/deserializer) PHY block is a new SoC block used
> in Freescale chips to support multiple serial interfaces, such as PCI
> Express, SGMII, SATA.
>
> Signed-off-by: Li Yang <leoli at freescale.com>
> ---
>  arch/powerpc/platforms/Kconfig   |    3 +
>  arch/powerpc/sysdev/Makefile     |    1 +
>  arch/powerpc/sysdev/fsl_serdes.c |  195 +++++++++++++++++++++++++++ 
> +++++++++++
>  3 files changed, 199 insertions(+), 0 deletions(-)
>  create mode 100644 arch/powerpc/sysdev/fsl_serdes.c
>
> diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/ 
> platforms/Kconfig
> index 229d355..0719e89 100644
> --- a/arch/powerpc/platforms/Kconfig
> +++ b/arch/powerpc/platforms/Kconfig
> @@ -315,6 +315,9 @@ config FSL_ULI1575
>  config CPM
>  	bool
>
> +config FSL_SERDES
> +	bool
> +

do you mind adding help here just something similar to the commit  
comment.  While a user might not see it, its useful documentation  
about what this is all about.

- k