[RFC/PATCH 14/16] MPIC MSI backend

[Eric W. Biederman]

Paul Mackerras <paulus at samba.org> writes:

> Eric W. Biederman writes:
>
>> I believe the ppc model is to allocate an interrupt source on their
>> existing interrupt controller and use that instead of the normal x86
>> case of having the MSI interrupt go transparently to the cpu.
>
> Do you mean that x86 cpus themselves can actually be the target of a
> write on the bus?  That's the first time I've heard of the CPU itself
> being a target for a bus operation.

Yes.  The cpu front side bus is packet based on all modern x86 processors,
and an irq message is one type of packet. 

> Or do you mean there is some piece of hardware in the northbridge (or
> elsewhere) that accepts the MSI message writes and asserts an
> interrupt line to the CPU?  That is basically what we have on PPC.

Nope, modern x86 cpus do not use external interrupt lines for normal
interrupts.

AMD cpus directly consume hypertransport and Intel cpus have a
proprietary but similarly capable protocol.

Eric