[PATCH RFC 0/7] "NAND on UPM" and related patches

[Anton Vorontsov]

On Wed, Dec 12, 2007 at 10:40:35AM -0600, Scott Wood wrote:
> On Mon, Dec 10, 2007 at 11:47:05PM +0300, Anton Vorontsov wrote:
> > 5 - FSL UPM infrastructure:
> > ---------------------------
> > UPM address register is shared among UPMs, so we have to do
> > proper locking. On the other hand, if we know that specific
> > board using only one UPM we could bypass locking, and gain some
> > performance win.
> 
> Not enough to be worth the complexity compared to the overhead of NAND
> access -- especially in the likely case of a non-SMP build.

I'm allowing UPM access from the IRQ handlers (because nothing prevents
this, so why deny?). Thus locks are needed even on non-SMP build, on
UP they aren't thrown away. Lockless variant occupy less than 30 lines of
code, so I'd rather keep it.

-- 
Anton Vorontsov
email: cbou at mail.ru
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