[PATCH 24/24] powerpc: Base support for 440SPe "Katmai" eval board
Stefan Roese
sr at denx.de
Sun Dec 2 23:35:33 EST 2007
On Sunday 02 December 2007, Stefan Roese wrote:
> > + PCIE0: pciex at d00000000 {
> > + device_type = "pci";
> > + #interrupt-cells = <1>;
> > + #size-cells = <2>;
> > + #address-cells = <3>;
> > + compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
> > + primary;
> > + port = <0>; /* port number */
>
> port = <1>;
Ups, sorry. <0> is correct here of course. "PCIE1" and "PCIE2" need different
numbers though.
> > + reg = <d 00000000 20000000 /* Config space access */
> > + c 10000000 00001000>; /* Registers */
> > + dcr-reg = <100 020>;
> > + sdr-base = <300>;
> > +
> > + /* Outbound ranges, one memory and one IO,
> > + * later cannot be changed
> > + */
> > + ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
> > + 01000000 0 00000000 0000000f 80000000 0 00010000>;
> > +
> > + /* Inbound 2GB range starting at 0 */
> > + dma-ranges = <42000000 0 0 0 0 0 80000000>;
> > +
> > + /* This drives busses 10 to 0x1f */
> > + bus-range = <10 1f>;
> > +
> > + /* Legacy interrupts (note the weird polarity). We are
> > + * de-swizzling here because the numbers are actually for
> > + * port of the root complex virtual P2P bridge. But I want
> > + * to avoid putting a node for it in the tree, so the numbers
> > + * below are basically de-swizzled numbers. The real slot is
> > + * on idsel 1, so the swizzling is new_pin = (pin % 4) + 1
> > + */
> > + interrupt-map-mask = <0000 0 0 7>;
> > + interrupt-map = <
> > + 0000 0 0 2 &UIC3 0 4 /* swizzled int A */
> > + 0000 0 0 3 &UIC3 1 4 /* swizzled int B */
> > + 0000 0 0 4 &UIC3 2 4 /* swizzled int C */
> > + 0000 0 0 1 &UIC3 3 4 /* swizzled int D */>;
> > + };
> > +
> > + PCIE1: pciex at d20000000 {
> > + device_type = "pci";
> > + #interrupt-cells = <1>;
> > + #size-cells = <2>;
> > + #address-cells = <3>;
> > + compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
> > + primary;
> > + port = <0>; /* port number */
>
> port = <2>;
That should be <1> now. And PCIE2 has this problem too.
Best regards,
Stefan
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