[PATCH] qe_ic: Do a sync when masking interrupts.

Michael R. Zucca mzucca at verizon.net
Tue Oct 24 01:30:52 EST 2006

>From: Li Yang-r58472 <LeoLi at freescale.com>
>But an i/o read will be considerably slower than a sync, and it is in
>the critical path of interrupt.  I have tested the patch under
>relatively heavy Ethernet load, and there is no spurious interrupt.
>Maybe it is because the device is an SOC device and MMIO store completes
>faster.  I'm wondering if there is a standard test method to show if the
>faster approach is sufficient or not.

All a sync tells you is that an I/O made it out of the CPU. The problem is, there may be other places a write could get hung up. For instance, sometimes devices sit behind a bridge with a write FIFO. In such a scenario, you can't be sure a write has made it to the device until you do a read to flush the FIFO.

If you're trying to figure out the minimum thing to do (eieio, sync, read-back, etc.) you have to understand what your system is doing between the store and the bits going into the register.

It may be that a sync is enough, but you won't know until you fully understand the system's bus/bridge topolgy between the CPU and the device.

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