where to find explanation of CP "RISC controller trap registers"?
dan at embeddededge.com
Sat Sep 18 07:33:21 EST 2004
On Sep 17, 2004, at 4:42 PM, Robert P. J. Day wrote:
> it all looks fairly straightforward, except in a couple cases where
> the CP RISC controller trap registers are set to, allegedly, enable
> the traps to get to [the patch].
They are not generally documented. As I have said in the past, along
the microcode is also documentation that explains how to use the patch.
The documentation states the order of initialization of various
CPM locations/registers and the values to write. You just do it.
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