where to find explanation of CP "RISC controller trap registers"?

[Robert P. J. Day]

   i'm working with the latest "bk pull" of the kernel source tree from 
ppc.bkbits.net/linuxppc-2.5, and i'm reading 
arch/ppc/8xx_io/micropatch.c to understand the intricacies of how 
patches get applied.

   it all looks fairly straightforward, except in a couple cases where 
the CP RISC controller trap registers are set to, allegedly, enable 
the traps to get to [the patch].

   example from micropatch.c:

#ifdef USE_IIC_PATCH
         /* Enable the traps to get to it.
         */
         commproc->cp_cpmcr1 = 0x802a;
         commproc->cp_cpmcr2 = 0x8028;
         commproc->cp_cpmcr3 = 0x802e;
         commproc->cp_cpmcr4 = 0x802c;

         /* Enable uCode fetches from DPRAM.
         */
         commproc->cp_rccr = 1;

         printk("I2C uCode patch installed\n");
#endif


   i've looked in vain in my copy of the MPC850 Family User's Manual 
for the breakdown of these trap registers and their values.  chapter 
18 on the Comm Processor maddeningly just seems to jump over these 
registers, unless i'm totally missing something.

   hints?

rday