Disabling interrupts on a SMP system

[Benjamin Herrenschmidt]

> I alway wondered why the decrementer interrupts are not listed, 
> actually. Perhaps even with a count of the decrementer interrupts
> which result in multiple updates of jiffies, because they indicate
> that something has avery high latency.
> 
> BTW, on my Pismo, the number of bad interrupts is amazing:
>
> .../...
>
> BAD:   21458276
> 
> in about one week uptime, but over half the time sleeping.
> 
> I have a fix for that, but it's not yet ready for submission. 
> I might find time over the week-end.

Ah ok, what is it ? Those seem to be "short" interrupts, they don't
happen on my tipb but they do happen on paul's older one (same mobo as
Pismo).

Looks like between clearing the irq source and exiting the handler, the
IRQ line stays asserted a bit longer or so ...

BTW, We should remove the cruft of early/late eoi too while we are at
it. A single "late" EOI is all we need. The MPIC will latch an edge irq
coming in between the ACK and the EOI and we don't want the CPU priority
to drop too early.

Ben.