Disabling interrupts on a SMP system

[Arrigo Benedetti]

Benjamin Herrenschmidt wrote:

>On Thu, 2004-10-28 at 16:58 -0700, Arrigo Benedetti wrote:
>
>  
>
>>To achieve real-time performance in a very critical section of code. 
>>Even after moving all the
>>interrupts to CPU0, there are still two interrupts running on CPU1 that 
>>are disturbing the
>>execution of the time-critical code:
>>    
>>
>
>  
>
>>118:         15      21134   OpenPIC   Level     IPI0 (call function)
>>119:        888        904   OpenPIC   Level     IPI1 (reschedule)
>>    
>>
>
>Those are normal, they are cross-CPU interrupts used internally by the
>kernel. There are also non-visible in that list the timer interrupts on
>both CPUs. You just can't do anything against these.
>
>  
>

Have these interrupts anything to do with the load balancer? I have 
disabled the load balancer code
in linux/sched.c (just commented out all the code in load_balance()).
Maybe the only solution is to write a kernel module?

-Arrigo