SCC UART configuration - GSMR_H[RFW]

Dan Malek dan at
Thu Oct 21 13:07:51 EST 2004

On Oct 20, 2004, at 9:28 PM, Jeff Angielski wrote:

> Was this done on purpose?

Kinda.  It was something I played with long ago when I
wrote the drivers.  I just never got back to testing the alternative
because I couldn't find a test method that would prove
one or the other was the better choice.

>   Is the documentation wrong?

I don't remember the details of the microcode anymore.  The
intention was to maximize the fifo depth and use the buffer
management controls to push the fifo to the BDs using
the max idle counter.  Maybe the SCC initialization just
thought I was stupid and set it internally anyway.

> FWIW, I noticed that u-boot sets this bit when it initializes the SCC
> for UART mode...

So, it seems either way works.  Maybe one of the Freescale
guys lurking here that was involved in the microcode development
can explain why.

	-- Dan

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