IBM 750GX SMP on Marvell Discovery II or III?

Gabriel Paubert paubert at
Wed May 12 21:53:30 EST 2004

On Wed, May 12, 2004 at 08:26:19PM +1000, Benjamin Herrenschmidt wrote:
> >
> > Are you sure? Since the cache lines are in the other processor memory,
> > they will be flushed to RAM when they are fetched by the processor,
> > provided that you can force the coherence bit on instruction fetches
> > (this is possible IIRC).
> Coherency of the data cache lines is one thing... getting the icbi
> broadcast is another. Normal coherency will not help if you don't get
> the icache of the other CPU to snoop your icbi and invalidate the trash
> it has in its icache.
> > As I said, I believe the real problem is multithreaded applications.
> Which isn't a simple problem...

Indeed, it is actually not solvable in a reasonable way, disabling
the icache being far too unreasonable ;-)

But my point was that Paul's example, one process being rescheduled
on another processor, is actually quite solvable (provided it is the
sole owner of the MM context). You don't lose much by flushing the
icache on a MEI system compared with the hardware overhead of all
the invalidations and flushing that will take place because of the
process switch.


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