IBM 750GX SMP on Marvell Discovery II or III?
benh at kernel.crashing.org
Wed May 12 20:26:19 EST 2004
> Are you sure? Since the cache lines are in the other processor memory,
> they will be flushed to RAM when they are fetched by the processor,
> provided that you can force the coherence bit on instruction fetches
> (this is possible IIRC).
Coherency of the data cache lines is one thing... getting the icbi
broadcast is another. Normal coherency will not help if you don't get
the icache of the other CPU to snoop your icbi and invalidate the trash
it has in its icache.
> As I said, I believe the real problem is multithreaded applications.
Which isn't a simple problem...
> > > My experience has been that MPC750s work in a SMP environment
> > > on a 60x bus. Maybe I was just lucky? The way I read the manual,
> > > they should work with a proper memory controller.
> > I think that the sorts of problems I am talking about wouldn't show up
> > very often. Generally I think that these problems would just cause
> > the system to be a bit flaky rather than stop it from working at all.
> I agree.
> > If you didn't have L2 caches that would make the problems show up less
> > frequently, too.
> I'm not so sure. Instruction fetches look into L2 caches. The main issue
> 1) are the instruction fetches marked coherent?
> 2) do you run multithreaded applications?
> If you answer yes and no, then I don't see any showstopper.
> > Regards,
> > Paul.
Benjamin Herrenschmidt <benh at kernel.crashing.org>
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