[PATCH] Workaround for 745x data corruption bug

[Brian Waite]

> Well that sucks (the bug, not the patch :).  Many people like to turn
> off coherency when using Marvell host bridges b/c they struggle
> performance-wise with coherency on (at least on some versions).
>
> One change to the patch, though.  According to the 7447/7457 errata doc,
> rev 1.2 doesn't have the bug.  The attached patch accounts for that.
>
> Mark
> --

Mark,

Looking at this errata, I don't think poeple using Marvell chips will
be affected by this errata.
I don't see this as impacting the IO subsystem only the internal MPX system. IE
using a 2 74xx system and not using the M bit. This race can also
occur on a single processor system with the M disabled, as it is in
Linux, but it has nothing to do with the memory controller mapping its
PCI<->mem windows as non cacheable. You should be able to boost the IO
throughput using non coherency without this errata impacting you any
more than it already is.

Anyone please correct me if I am wrong because I need to know.

Thanks
Brian

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