[PATCH] Workaround for 745x data corruption bug

[Sven Luther]

On Mon, Aug 02, 2004 at 11:20:30AM -0700, Mark A. Greer wrote:
> Adrian Cox wrote:
>
> >Recently released errata documents show a new bug in all 745x family
> >processors. This can cause data corruption when memory is mapped
> >non-coherent and one of these conditions is true:
> >1) L2 hardware prefetch is enabled (as it is in Linux)
> >2) instructions and data are fetched from the same or adjacent cache
> >lines.
> >
> >The attached patch adds a workaround, by setting CPU_FTR_NEED_COHERENT
> >on all 745x processors.
> >
>
> Well that sucks (the bug, not the patch :).  Many people like to turn
> off coherency when using Marvell host bridges b/c they struggle
> performance-wise with coherency on (at least on some versions).
>
> One change to the patch, though.  According to the 7447/7457 errata doc,
> rev 1.2 doesn't have the bug.  The attached patch accounts for that.

Notice that there are rev 1.1 7447s around, and that benh's patch does include
support for both the 1.1 and the 1.2 ones.

Friendly,

Sven Luther

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