linuxppc_2_4_devel patch for 745x cache invalidate (in bootwrapper)

[Mark A. Greer]

There are some differences in the L2CR register between the 75x/74x0 and
the 745x processors that weren't accounted for in the arch/ppc/boot/...
bootwrapper code.  Also, there was no bootwrapper code to turn off L3
cache on 745x processors.

The attached patch does the following:
a) Modify arch/ppc/boot/common/util.S:_setup_L2CR to poll on the proper
bit when doing an L2 global invalidate.  On 75x & 74x0 processors, that
means polling the L2IP bit; on 745x processors, that means polling on
the L2I bit.  BTW, the code is already correct in arch/ppc/kernel/l2cr.S.
b) Add arch/ppc/boot/common/util.S:_setup_l3CR routine which turns off
L3 cache and does a global invalidate on it.
c) Modify arch/ppc/boot/simple/head.S:start_ to call _setup_L3CR if
running on a 745x processor.  This is #ifdef'd out for all platforms
except CONFIG_FORCE, CONFIG_K2, CONFIG_EV64260, and CONFIG_PAL4--the
#ifdef was already there.

This patch has been successfully tested on a few platforms inside
MontaVista.  However, those of you that use the bootwrapper on 745x
platforms may want to test it as well.  If you do test it, please
respond to this email with your results.  If there are no responses by
mid-week next week, say, I will assume the patch is fine and ask that it
get applied to the public linuxppc_2_4_devel source.

Thanks,

Mark
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