MPC7455 and lwarx
wilhardt at synergymicro.com
Thu Nov 28 04:11:37 EST 2002
> Why do you want to use these instructions on a data space that isn't
> cached? Further, why are you running this class of processor with
> uncached memory?
I have a "shared memory" region that is used between VME boards in
a chassis. The "master pool" is located on the system controller in DRAM.
In order to maintain coherency between the boards, I have marked the region
as non cached. This was fine for non-MPC745x boards. Time for a redesign...
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