MPC7455 and lwarx

[Dan Malek]

Gabriel Paubert wrote:

> No, it is documented somewhere in Motorola docs that lwarx/stwcx. only
> work on writeback cacheable space. Earlier processors allow non-cacheable
> space, I believe that this restriction was introduced with the 7440/7450.

There are implementation options in the PowerPC specification that will
produce different "working" behavior when these instructions are not
used properly.  As Gabriel mentioned, the programmer interface specifies
these instrucitons work properly only on cached, writeback data spaces.
This is because the finest granularity implementation is a cache line and
the synchronization information is stored in the cache tag.  Processors
that aren't MP capable, like the 4xx, appear to operate as if they have
a single global flag to support lwarx/stwcx so the cache mode of the
desitination address (and the address itself) is irrelevant.  This
"restriction" has been around forever, MP systems won't work properly
without it (and all 6xx and "bigger" cores are MP capable).

Why do you want to use these instructions on a data space that isn't
cached?  Further, why are you running this class of processor with
uncached memory?

Thanks.


	-- Dan


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