Changes to gt64260 PCI arbiter enable code

[mod+linuxppc-dev at MissionCriticalLinux.com]

Please introduce these changes into the linuxppc
sources in order that the existing generic
gt64260 setup code be usable on platforms other
than the Galileo Eval Board.

The current gt64260 setup contains incorrect
assumptions about internal arbiter setup based
solely upon the detected chip revision, when
this decision is actually platform-dependent;
such code is moved to platform-specific files.

Patch also corrects some comments.


Regards,
          Michael O'Donnell
        Mission Critical Linux


-------------- next part --------------
===== arch/ppc/kernel/gt64260_common.c 1.6 vs edited =====
--- 1.6/arch/ppc/kernel/gt64260_common.c	Mon Dec 17 17:09:20 2001
+++ edited/arch/ppc/kernel/gt64260_common.c	Wed Jan  2 16:28:21 2002
@@ -334,10 +356,6 @@
 		GT64260_RESET_REG_BITS(GT64260_PCI_0_CMD, (BIT4 | BIT5 | BIT9));
 		GT64260_RESET_REG_BITS(GT64260_PCI_1_CMD, (BIT4 | BIT5 | BIT9));
 
-		/* FEr#35 */
-		GT64260_RESET_REG_BITS(GT64260_PCI_0_ARBITER_CNTL, BIT31);
-		GT64260_RESET_REG_BITS(GT64260_PCI_1_ARBITER_CNTL, BIT31);
-
 		/* FEr#54 */
 		GT64260_RESET_REG_BITS(GT64260_CPU_SNOOP_BASE_0, 0xfffcf000);
 		GT64260_RESET_REG_BITS(GT64260_CPU_SNOOP_BASE_1, 0xfffcf000);
@@ -346,21 +364,15 @@
 
 		/* R#18 */
 		GT64260_SET_REG_BITS(GT64260_SDRAM_CONFIG, BIT26);
-	}
-	else if (gt64260_revision == GT64260A) {
+
+	} else if (gt64260_revision == GT64260A) {
 		/* R#18 */
 		GT64260_SET_REG_BITS(GT64260_SDRAM_CONFIG, BIT26);
 
-		/* ?? */
-		GT64260_SET_REG_BITS(GT64260_PCI_0_ARBITER_CNTL, BIT31);
-		GT64260_SET_REG_BITS(GT64260_PCI_1_ARBITER_CNTL, BIT31);
-
 		/* No longer errata so turn on */
 		GT64260_SET_REG_BITS(GT64260_PCI_0_CMD, (BIT4 | BIT5 | BIT9));
 		GT64260_SET_REG_BITS(GT64260_PCI_1_CMD, (BIT4 | BIT5 | BIT9));
 	}
-
-	return;
 } /* gt64260_check_errata() */
 
 
@@ -385,16 +397,14 @@
 		/* Set up the window on the CPU side */
 		GT64260_REG_WRITE(bot_reg, (base_addr >> 20) | other_bits);
 		GT64260_REG_WRITE(top_reg, (base_addr + size - 1) >> 20);
-
-	}
-	else { /* Disable window */
-		GT64260_REG_WRITE(bot_reg, 0x00000fff | other_bits);
+	} else { /* Disable window */
 		GT64260_REG_WRITE(top_reg, 0x00000000);
+		GT64260_REG_WRITE(bot_reg, 0x00000fff | other_bits);
 	}
 
 	val = GT64260_REG_READ(bot_reg); /* Flush FIFO */
 	return 0;
-} /* gt64260_cpu_set_32bit_window() */
+} /* gt64260_set_32bit_window() */
 
 static int
 gt64260_set_64bit_window(u32 base_addr_hi,
@@ -418,7 +428,7 @@
 	}
 
 	return rc;
-} /* gt64260_cpu_set_64bit_window() */
+} /* gt64260_set_64bit_window() */
 
 
 /*
@@ -492,7 +502,7 @@
 				      GT64260_CPU_BOOT_CS_DECODE_0_TOP);
 
 	return rc;
-} /* gt64260_cpu_scs_set_window() */
+} /* gt64260_cpu_boot_set_window() */
 
 /*
  * gt64260_cpu_set_pci_io_window()
===== arch/ppc/platforms/ev64260_pci.c 1.7 vs edited =====
--- 1.7/arch/ppc/platforms/ev64260_pci.c	Fri Dec 21 03:51:01 2001
+++ edited/arch/ppc/platforms/ev64260_pci.c	Wed Jan  2 16:27:36 2002
@@ -122,6 +122,20 @@
 		return rc;
 	}
 
+	/*
+	 * Enabling of PCI internal-vs-external arbitration
+	 * is a platform- and errata-dependent decision.
+	 */
+	if( gt64260_revision == GT64260 )  {
+		/* FEr#35 */
+		GT64260_RESET_REG_BITS(GT64260_PCI_0_ARBITER_CNTL, BIT31);
+		GT64260_RESET_REG_BITS(GT64260_PCI_1_ARBITER_CNTL, BIT31);
+	} else if( gt64260_revision == GT64260A )  {
+		GT64260_SET_REG_BITS(GT64260_PCI_0_ARBITER_CNTL, BIT31);
+		GT64260_SET_REG_BITS(GT64260_PCI_1_ARBITER_CNTL, BIT31);
+	}
+
+
 	GT64260_SET_REG_BITS(GT64260_CPU_MASTER_CNTL, BIT9); /* Only 1 cpu */
 
 	/* SCS windows not disabled above, disable all but SCS 0 */