PCI address translation design notes

[Allen Curtis]

Are there notes regarding the host bridge initialization and the various
address translations? I have read the Documentation/pci.txt file and it
pertains to PCI device drivers.

Any information regarding the setup of:
Host to PCI bus I/O and Memory resource configuration
PCI bus to Host resource configuration
PCI device to device resource access

The basic problem is that the views between the buses does not have to be,
and in my case are not orthogonal.

I.e.
Host to PCI Memory
base = 0x48000000

PCI to Host Memory
base = 0x40000000

PCI device to device memory
base = 0x00000000

TIA


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