[PATCH 08/10] spi: aspeed: Calibrate read timings

Pratyush Yadav p.yadav at ti.com
Fri Feb 25 20:18:09 AEDT 2022

On 14/02/22 10:42AM, Cédric Le Goater wrote:
> To accommodate the different response time of SPI transfers on different
> boards and different SPI NOR devices, the Aspeed controllers provide a
> set of Read Timing Compensation registers to tune the timing delays
> depending on the frequency being used. The AST2600 SoC has one of
> these registers per device. On the AST2500 and AST2400 SoCs, the
> timing register is shared by all devices which is a bit problematic to
> get good results other than for one device.
> The algorithm first reads a golden buffer at low speed and then performs
> reads with different clocks and delay cycle settings to find a breaking
> point. This selects a default good frequency for the CEx control register.
> The current settings are bit optimistic as we pick the first delay giving
> good results. A safer approach would be to determine an interval and
> choose the middle value.
> Due to the lack of API, calibration is performed when the direct mapping
> for reads is created.

The dirmap_create mapping says nothing about _when_ it should be called. 
So there is no guarantee that it will only be called after the flash is 
fully initialized. I suggest you either make this a requirement of the 
API, or create a new API that guarantees it will only be called after 
the flash is initialized, like [0].

[0] https://patchwork.ozlabs.org/project/linux-mtd/patch/20210311191216.7363-2-p.yadav@ti.com/

> Cc: Pratyush Yadav <p.yadav at ti.com>
> Signed-off-by: Cédric Le Goater <clg at kaod.org>
> ---

Pratyush Yadav
Texas Instruments Inc.

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