[PATCH -next 1/2] media: aspeed: refine hsync/vsync polarity setting logic
Jae Hyun Yoo
jae.hyun.yoo at linux.intel.com
Fri Sep 13 03:04:16 AEST 2019
On 9/11/2019 10:33 PM, Andrew Jeffery wrote:
> On Wed, 11 Sep 2019, at 04:37, Jae Hyun Yoo wrote:
>> This commit refines hsync/vsync polarity setting logic by making
>> also clearing register bits possible based on probed sync state
> That was tough to parse, but I think I understand. Trying to rephrase:
> Enable clearing of hsync/vsync plarity bits based on probed sync state.
> What was the issue that drove the change? Do you know why it was done
> the way it was prior to this patch?
Because this driver detects weird resolutions sometimes. Investigated
that it uses
aspeed_video_update(video, VE_CTRL, 0, ctrl);
so only setting of polarity bits is available. Means that clearing of
the bits isn't available so it can't set back the polarities to normal.
To fix the issue, this patch makes it use
aspeed_video_write(video, VE_CTRL, ctrl);
instead of above one with adding bit masking code changes.
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