Re: [PATCH -next 1/2] media: aspeed: refine hsync/vsync polarity setting logic
andrew at aj.id.au
Thu Sep 12 15:33:00 AEST 2019
On Wed, 11 Sep 2019, at 04:37, Jae Hyun Yoo wrote:
> This commit refines hsync/vsync polarity setting logic by making
> also clearing register bits possible based on probed sync state
That was tough to parse, but I think I understand. Trying to rephrase:
Enable clearing of hsync/vsync plarity bits based on probed sync state.
What was the issue that drove the change? Do you know why it was done
the way it was prior to this patch?
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