[PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs

[Stephen Boyd]

Quoting Joel Stanley (2019-11-25 16:59:19)
> Hi Stephen,
> 
> On Thu, 10 Oct 2019 at 23:41, Joel Stanley <joel at jms.id.au> wrote:
> >
> > On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew at aj.id.au> wrote:
> > >
> > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a
> > > single gate for each MAC.
> > >
> > > Signed-off-by: Andrew Jeffery <andrew at aj.id.au>
> >
> > Reviewed-by: Joel Stanley <joel at jms.id.au>
> 
> I noticed this one hasn't been applied to clk-next.
> 

It's marked awaiting upstream in my UI. I think it was some patch that
might have come through your PR?